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32 résultats
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Prospects for energy-efficient edge computing with integrated HfO 2-based ferroelectric devicesIFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SOC), Oct 2018, Verona, Italy. ⟨10.1109/VLSI-SoC.2018.8644809⟩
Communication dans un congrès
hal-01916992v1
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Why neuromorphic computing need novel 3D technologies? A view from FVLLMONTI European project consortium (Invited)High Performance Embedded Architecture and Compilation, Computing Systems Week, (HiPEAC CSW) Autumn 2021, Oct 2021, Lyon, France
Communication dans un congrès
hal-03408071v1
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System architectures and new computing paradigmsjournée thématique In-Memory-Computing: from Device to Programming Model, Feb 2021, Paris, France
Communication dans un congrès
hal-03142107v1
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NEUROPULS: NEUROmorphic energy-efficient secure accelerators based on Phase change materials aUgmented siLicon photonicSETS 2023 - IEEE European Test Symposium, IEEE, May 2023, Venise, Italy. ⟨10.48550/arXiv.2305.03139⟩
Communication dans un congrès
hal-04103942v1
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Granularity Exploration for Logic in Memory2020
Autre publication scientifique
hal-02732764v1
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A Logic Cell Design and routing Methodology Specific to VNWFET2022 20th IEEE Interregional NEWCAS Conference (NEWCAS), Jun 2022, Quebec City, Canada. pp.460-464, ⟨10.1109/NEWCAS52662.2022.9842100⟩
Communication dans un congrès
hal-03864493v1
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3D Logic Cells Design and Results Based on Vertical NWFET Technology Including Tied Compact ModelVLSI-SoC: Design Trends, 621, Springer International Publishing, pp.301-321, 2021, IFIP Advances in Information and Communication Technology, ⟨10.1007/978-3-030-81641-4_14⟩
Chapitre d'ouvrage
hal-03371673v1
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Correlation Analysis of the Power Consumption applied to IP watermark verification.Colloque national du GDR SOC-SIP, Jun 2014, Paris, France
Communication dans un congrès
ujm-01015290v1
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IP Watermark Verification Based on Power Consumption Analysis27th IEEE International Systems-on-Chip Conference, SOCC 2014, Sep 2014, Las Vegas, United States. pp.330-335
Communication dans un congrès
ujm-01063085v1
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Identification of IP control units by state encoding and side channel verificationMicroprocessors and Microsystems: Embedded Hardware Design , 2016, 47 (Part A), pp.11-22. ⟨10.1016/j.micpro.2016.02.019⟩
Article dans une revue
hal-01382714v1
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A FeFET-Based Hybrid Memory Accessible by Content and by AddressIEEE Journal on Exploratory Solid-State Computational Devices and Circuits, 2022, 8 (1), pp.19-26. ⟨10.1109/JXCDC.2022.3168057⟩
Article dans une revue
hal-03727669v1
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Enhanced TERO-PUF Implementations and Characterization on FPGAs the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, ACM, Feb 2016, Monterey, United States. ⟨10.1145/2847263.2847298⟩
Communication dans un congrès
hal-01285993v1
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Design, Evaluation and Optimization of Physical Unclonable Functions based on Transient Effect Ring OscillatorsIEEE Transactions on Information Forensics and Security, 2016, ⟨10.1109/TIFS.2016.2524666⟩
Article dans une revue
hal-01279172v1
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Emerging Technologies: Challenges and Opportunities for Logic Synthesis2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), Apr 2021, Vienna (virtual), Austria. pp.93-98, ⟨10.1109/DDECS52668.2021.9417062⟩
Communication dans un congrès
hal-03266914v1
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Conception de matériel salutaire pour lutter contre la contrefaçon et le vol de circuits intégrésMicro et nanotechnologies/Microélectronique. Université de Lyon, 2016. Français. ⟨NNT : 2016LYSES058⟩
Thèse
tel-02078791v1
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Evariste III: A new multi-FPGA system for fair benchmarking of hardware dependent cryptographic primitivesWorkshop on Cryptographic Hardware and Embedded Systems, CHES 2015, Sep 2015, st-malo, France. 2015
Poster de conférence
ujm-01219840v1
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Design and Characterization of the TERO-PUF on SRAM FPGAsIEEE Computer Society Annual Symposium on VLSI (ISVLSI), Jul 2016, Pittsburgh, United States. pp.134-139, ⟨10.1109/ISVLSI.2016.18⟩
Communication dans un congrès
hal-01382948v1
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3D logic cells design and results based on Vertical NWFET technology including tied compact model28th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SOC) 2020, Oct 2020, Salt Lake City (virtual), United States. ⟨10.1109/VLSI-SOC46417.2020.9344094⟩
Communication dans un congrès
hal-03166674v1
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Processeur sécurisé et reconfigurable utilisant des technologies émergentesWorkshop interdisciplinaire sur la sécurité globale (WISG), Jan 2022, Bordeaux, France
Poster de conférence
hal-03549070v1
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3D Logic circuit design oriented electrothermal modeling of vertical junctionless nanowire FETsIEEE Journal on Exploratory Solid-State Computational Devices and Circuits, 2023, 9 (2), pp.116 - 123. ⟨10.1109/JXCDC.2023.3309502⟩
Article dans une revue
hal-04230911v1
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Modelling of vertical and ferroelectric junctionless technology for efficient 3D neural network compute cube dedicated to embedded artificial intelligence (Invited)67th Annual IEEE International Electron Devices Meeting (IEDM 2021), Dec 2021, San Fransisco, United States. ⟨10.1109/IEDM19574.2021.9720572⟩
Communication dans un congrès
hal-03408078v1
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Side Channel Analysis, an Efficient Ally for IP ProtectionLilian Bossuet; Lionel Torres. Foundations of Hardware IP Protection, Springer International Publishing, pp.85-104, 2017, 978-3-319-50378-3. ⟨10.1007/978-3-319-50380-6_5⟩
Chapitre d'ouvrage
hal-01450628v1
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Ultra-Lightweight Implementation in Area of Block CiphersLilian Bossuet; Lionel Torres. Foundations of Hardware IP Protection, Springer International Publishing, pp.117-203, 2017, 978-3-319-50378-3. ⟨10.1007/978-3-319-50380-6_9⟩
Chapitre d'ouvrage
hal-01450637v1
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Area-oriented comparison of lightweight block ciphers implemented in hardware for the activation mechanism in the anti-counterfeiting schemesInternational Journal of Circuit Theory and Applications, 2017, 45 (2), pp.274-291. ⟨10.1002/cta.2288⟩
Article dans une revue
hal-01450389v1
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Study of a Battery-less Near Field Communicating Sensor Network with ContactLess SimulatorInternational Journal On Advances in Telecommunications, 2018
Article dans une revue
hal-01971689v1
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FeFET based Logic-in-Memory: an overview2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), Jun 2021, Montpellier, France. pp.1-6, ⟨10.1109/DTIS53253.2021.9505078⟩
Communication dans un congrès
hal-03323883v1
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Hardware Emulation of FeFET On FPGA2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Jul 2022, Nicosia, Cyprus. pp.380-385, ⟨10.1109/ISVLSI54635.2022.00085⟩
Communication dans un congrès
hal-04138756v1
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Identification of Embedded Control Units by State Encoding and Power Consumption AnalysisACM/SIGAPP Symposium On Applied Computing, Apr 2015, Salamanca, Spain. ⟨10.1145/2695664.2695963⟩
Communication dans un congrès
hal-01170956v1
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Verification of IP Watermark using Correlation AnalysisInternational Workshops on Cryptographic Architectures Embedded in Reconfigurable Devices (Cryptarchi 2014), Jun 2014, Annecy, France. pp.13
Communication dans un congrès
ujm-01011317v1
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On the Security Evaluation of the ARM TrustZone Extension in a Heterogeneous SoC30th IEEE INTERNATIONAL SYSTEM-ON-CHIP CONFERENCE, Sep 2017, Munich, Germany
Communication dans un congrès
ujm-01589573v1
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