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  • IdHAL : bruno-rouzeyre

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186

Publications of Bruno Rouzeyre


Journal articles27 documents

  • Mathieu da Silva, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre. Preventing Scan Attacks on Secure Circuits Through Scan Chain Encryption. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE, 2019, 38 (3), pp.538-550. ⟨10.1109/TCAD.2018.2818722⟩. ⟨lirmm-01867245⟩
  • Emanuele Valea, Mathieu da Silva, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre. Stream vs Block ciphers for scan encryption. Microelectronics Journal, Elsevier, 2019, 86, pp.65-76. ⟨10.1016/j.mejo.2019.02.019⟩. ⟨lirmm-02306938⟩
  • J.-M. Dutertre, Vincent Beroulle, Philippe Candelier, Stephan de Castro, Louis-Barthelemy Faber, et al.. Sensitivity to Laser Fault Injection: CMOS FD-SOI vs. CMOS bulk. IEEE Transactions on Device and Materials Reliability, Institute of Electrical and Electronics Engineers, 2019, 19 (1), pp.6-15. ⟨10.1109/TDMR.2018.2886463⟩. ⟨hal-01971932⟩
  • Emanuele Valea, Mathieu da Silva, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. A Survey on Security Threats and Countermeasures in IEEE Test Standards. IEEE Design & Test, IEEE, 2019, 36 (3), pp.95-116. ⟨10.1109/MDAT.2019.2899064⟩. ⟨hal-02166858⟩
  • Sophie Dupuis, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre. Protection against Hardware Trojans with Logic Testing: Proposed Solutions and Challenges Ahead. IEEE Design & Test, IEEE, 2018, 35 (2), pp.73-90. ⟨10.1109/MDAT.2017.2766170⟩. ⟨lirmm-01688166⟩
  • Raphael Andreoni Camponogara-Viera, Jean-Max Dutertre, Marie-Lise Flottes, Olivier Potin, Giorgio Di Natale, et al.. Assessing Body Built-In Current Sensors for Detection of Multiple Transient Faults. Microelectronics Reliability, Elsevier, 2018, 88-90 (29th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF 2018)), pp.128-134. ⟨10.1016/j.microrel.2018.07.111⟩. ⟨hal-01893676⟩
  • Stephan de Castro, Jean-Max Dutertre, Bruno Rouzeyre, Giorgio Di Natale, Marie-Lise Flottes. Frontside Versus Backside Laser Injection: A Comparative Study. ACM Journal on Emerging Technologies in Computing Systems, Association for Computing Machinery, 2016, Special Issue on Secure and Trustworthy Computing, 13 (1), pp.7. ⟨10.1145/2845999⟩. ⟨lirmm-01444121⟩
  • Feng Lu, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Multi-Level Ionizing-Induced Transient Fault Simulator. Information Security Journal: A Global Perspective, Taylor & Francis, 2014, 22 (5-6), pp.251-264. ⟨10.1080/19393555.2014.891280⟩. ⟨lirmm-01075393⟩
  • Sophie Dupuis, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. On the Effectiveness of Hardware Trojan Horse Detection via Side-Channel Analysis. Information Security Journal: A Global Perspective, Taylor & Francis, 2014, Trustworthy Manufacturing and Utilization of Secure Devices, 22 (5-6), pp.226-236. ⟨10.1080/19393555.2014.891277⟩. ⟨lirmm-00991362⟩
  • Jean da Rolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Thwarting Scan-Based Attacks on Secure-ICs with On-Chip Comparison. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE, 2014, 22 (4), pp.947-951. ⟨10.1109/TVLSI.2013.2257903⟩. ⟨lirmm-00841650⟩
  • Jean-Max Dutertre, Rodrigo Possamai Bastos, Olivier Potin, Marie-Lise Flottes, Bruno Rouzeyre, et al.. Improving the ability of Bulk Built-In Current Sensors to detect Single Event Effects by using triple-well CMOS. Microelectronics Reliability, Elsevier, 2014, 54 (9-10), pp.2289-2294. ⟨10.1016/j.microrel.2014.07.151⟩. ⟨emse-01094805⟩
  • Jean da Rolt, Amitabh Das, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, et al.. Test versus Security: Past and Present. IEEE Transactions on Emerging Topics in Computing, Institute of Electrical and Electronics Engineers, 2014, 2 (1), pp.50-62. ⟨10.1109/TETC.2014.2304492⟩. ⟨lirmm-00989627⟩
  • Jean da Rolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. A Novel Differential Scan Attack on Advanced DFT Structures. ACM Transactions on Design Automation of Electronic Systems, Association for Computing Machinery, 2013, 18 (4), pp.58. ⟨10.1145/2505014⟩. ⟨lirmm-01075410⟩
  • Rodrigo Possamai Bastos, Giorgio Di Natale, Marie-Lise Flottes, Feng Lu, Bruno Rouzeyre. A New Recovery Scheme Against Short-to-Long Duration Transient Faults in Combinational Logic. Journal of Electronic Testing, Springer Verlag, 2013, pp.001-010. ⟨10.1007/s10836-013-5359-y⟩. ⟨lirmm-00838389⟩
  • Amitabh Das, Jean da Rolt, Santosh Ghosh, Stefaan Seys, Sophie Dupuis, et al.. Secure JTAG Implementation Using Schnorr Protocol. Journal of Electronic Testing, Springer Verlag, 2013, 29 (2), pp.193-209. ⟨10.1007/s10836-013-5369-9⟩. ⟨lirmm-00837904⟩
  • Jean-Max Dutertre, Rodrigo Possamai Bastos, Olivier Potin, Marie-Lise Flottes, Bruno Rouzeyre, et al.. Sensitivity tuning of a bulk built-in current sensor for optimal transient-fault detection. Microelectronics Reliability, Elsevier, 2013, European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, 53 (9), pp.1320-1324. ⟨10.1016/j.microrel.2013.07.069⟩. ⟨emse-01100723⟩
  • Jean da Rolt, Amitabh Das, Santos Ghosh, Giorgio Di Natale, Marie-Lise Flottes, et al.. Scan attacks on side-channel and fault attack resistant public-key implementations. Journal of Cryptographic Engineering, Springer, 2012, 2 (4), pp.207-219. ⟨10.1007/s13389-012-0045-z⟩. ⟨lirmm-00805687⟩
  • Rodrigo Possamai Bastos, Frank Sill Torres, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Novel Transient-Fault Detection Circuit Featuring Enhanced Bulk Built-in Current Sensor with Low-Power Sleep Mode. Microelectronics Reliability, Elsevier, 2012, 52 (9-10), pp.1781-1786. ⟨10.1016/j.microrel.2012.06.149⟩. ⟨lirmm-00715117⟩
  • Giorgio Di Natale, Doulcier Marion, Marie-Lise Flottes, Bruno Rouzeyre. A Reliable Architecture for Parallel Implementations of the Advanced Encryption Standard. Journal of Electronic Testing, Springer Verlag, 2009, 25 (4-5), pp.269-278. ⟨10.1007/s10836-009-5106-6⟩. ⟨lirmm-00423026⟩
  • Giorgio Di Natale, Marion Doulcier, Marie-Lise Flottes, Bruno Rouzeyre. Self-Test Techniques for Crypto-Devices. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE, 2009, 18 (2), pp.329-333. ⟨10.1109/TVLSI.2008.2010045⟩. ⟨lirmm-00365359⟩
  • David Hely, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre. Securing Scan Control in Crypto Chips. Journal of Electronic Testing, Springer Verlag, 2007, 23 (5), pp.457-464. ⟨10.1007/s10836-007-5000-z⟩. ⟨lirmm-00186353⟩
  • Solaiman Rahim, Bruno Rouzeyre, Lionel Torres. A Flip-Flop Matching Engine to Verify Sequential Optimizations. Computing and Informatics, Slovak University Press, Bratislava, 2004, 24 (5-6), pp.437-460. ⟨lirmm-00108550⟩
  • Marie-Lise Flottes, Bruno Rouzeyre, Leo Volpe. Improving Datapath Testability by Modifying Controller Specification. VLSI Design, Hindawi Publishing Corporation, 2002, 15 (2), pp.491-498. ⟨10.1080/1065514021000012101⟩. ⟨lirmm-00268581⟩
  • David Berthelot, Marie-Lise Flottes, Bruno Rouzeyre. A Method for Trading Test Time, Area and Fault Coverage in Datapath BIST Synthesis. Journal of Electronic Testing, Springer Verlag, 2001, 17 (3/4), pp.331-339. ⟨10.1023/A:1012227715327⟩. ⟨lirmm-02288800⟩
  • David Berthelot, Marie-Lise Flottes, Bruno Rouzeyre. BISTing Datapaths under Heterogeneous Test Schemes. Journal of Electronic Testing, Springer Verlag, 1999, 14 (1/2), pp.115-123. ⟨10.1023/A:1008309625123⟩. ⟨lirmm-02288809⟩
  • Marie-Lise Flottes, D. Hammad, Bruno Rouzeyre. Improving Testability of Non-Scan Designs during Behavioral Synthesis. Journal of Electronic Testing, Springer Verlag, 1997, 11 (1), pp.29-42. ⟨10.1023/A:1008243700142⟩. ⟨lirmm-02288852⟩
  • Bruno Rouzeyre, Toufic Ezzedine, Georges Sagnes. Operators allocation in the silicon compiler SCOOP. Integration, the VLSI Journal, Elsevier, 1989, 8 (2), pp.99-109. ⟨10.1016/0167-9260(89)90043-6⟩. ⟨lirmm-02288867⟩

Conference papers115 documents

  • Emanuele Valea, Mathieu da Silva, Marie-Lise Flottes, Giorgio Di Natale, Sophie Dupuis, et al.. Providing Confidentiality and Integrity in Ultra Low Power IoT Devices. DTIS: Design & Technology of Integrated Systems In Nanoscale Era, Apr 2019, Mykonos, Greece. ⟨10.1109/DTIS.2019.8735090⟩. ⟨hal-02166920⟩
  • Marc Merandat, Vincent Reynaud, Emanuele Valea, Jerome Quevremont, Nicolas Valette, et al.. A Comprehensive Approach to a Trusted Test Infrastructure. IVSW: International Verification and Security Workshop, Jul 2019, Rhodes, Greece. ⟨lirmm-02306980⟩
  • Emanuele Valea, Mathieu da Silva, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre. Encryption-Based Secure JTAG. DDECS: Design and Diagnostics of Electronic Circuits Systems, Apr 2019, Cluj-Napoca, Romania. ⟨10.1109/DDECS.2019.8724654⟩. ⟨hal-02149061⟩
  • Emanuele Valea, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre. Stream Cipher Based Encryption in IEEE Test Standards. 8th Workshop on Trustworthy Manufacturing and Utilization of Secure Devices (TRUDEVICE), May 2019, Baden Baden, Germany. ⟨hal-02506743⟩
  • Emanuele Valea, Mathieu da Silva, Giorgio Di Natale, Marie-Lise Flottes, Sophie Dupuis, et al.. SECCS: SECure Context Saving for IoT Devices. DTIS: Design and Technology of Integrated Systems in Nanoscale Era, Apr 2018, Taormina, Italy. ⟨hal-01740173⟩
  • Mathieu da Silva, Emanuele Valea, Marie-Lise Flottes, Sophie Dupuis, Giorgio Di Natale, et al.. Encryption of test data: which cipher is better?. PRIME: PhD Research in Microelectronics and Electronics, Jul 2018, Prague, Czech Republic. pp.85-88, ⟨10.1109/PRIME.2018.8430366⟩. ⟨lirmm-01867249⟩
  • Mathieu da Silva, Emanuele Valea, Marie-Lise Flottes, Sophie Dupuis, Giorgio Di Natale, et al.. A new secure stream cipher for scan chain encryption. IVSW: International Verification and Security Workshop, Jul 2018, Platja d’Aro, Spain. ⟨lirmm-01867256⟩
  • Mathieu da Silva, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre. Does stream cipher-based scan chains encryption really prevent scan attacks?. TRUDEVICE Workshop, Mar 2018, Dresden, Germany. ⟨lirmm-01867286⟩
  • Jean-Max Dutertre, Vincent Beroulle, Philippe Candelier, Louis-Barthelemy Faber, Marie-Lise Flottes, et al.. The case of using CMOS FD-SOI rather than CMOS bulk to harden ICs against laser attacks. IOLTS: International On-Line Testing Symposium, Jul 2018, Platja d’Aro, Spain. pp.214-219, ⟨10.1109/IOLTS.2018.8474230⟩. ⟨emse-01856000⟩
  • Jean-Max Dutertre, Vincent Beroulle, Philippe Candelier, Stephan de Castro, Louis-Barthelemy Faber, et al.. Laser fault injection at the CMOS 28 nm technology node: an analysis of the fault model. FDTC: Fault Diagnosis and Tolerance in Cryptography, Sep 2018, Amsterdam, Netherlands. pp.1-6, ⟨10.1109/FDTC.2018.00009⟩. ⟨emse-01856008⟩
  • Mathieu da Silva, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre. Experimentations on scan chain encryption with PRESENT. IVSW: International Verification and Security Workshop, Jul 2017, Thessaloniki, Greece. pp.45-50, ⟨10.1109/IVSW.2017.8031543⟩. ⟨lirmm-01699258⟩
  • Mathieu da Silva, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre, Paolo Prinetto, et al.. Scan chain encryption for the test, diagnosis and debug of secure circuits. ETS: European Test Symposium, May 2017, Limassol, Cyprus. ⟨10.1109/ETS.2017.7968248⟩. ⟨lirmm-01699254⟩
  • Mathieu da Silva, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre. Scan Chain Encryption. DOCTIS: Journée des Doctorants de l’école doctorale I2S, 2017, Montpellier, France. ⟨lirmm-01867277⟩
  • Giorgio Di Natale, Marie-Lise Flottes, Sophie Dupuis, Bruno Rouzeyre. Hacking the Control Flow error detection mechanism. IVSW: International Verification and Security Workshop, Jul 2017, Thessaloniki, Greece. pp.51-56, ⟨10.1109/IVSW.2017.8031544⟩. ⟨lirmm-01700739⟩
  • Papa-Sidy Ba, Sophie Dupuis, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre. Using Outliers to Detect Stealthy Hardware Trojan Triggering?. IVSW: International Verification and Security Workshop, Jul 2016, Sant Feliu de Guixols, France. ⟨lirmm-01347119⟩
  • Papa-Sidy Ba, Sophie Dupuis, Manikandan Palanichamy, Marie-Lise Flottes, Giorgio Di Natale, et al.. Hardware Trust through Layout Filling: a Hardware Trojan Prevention Technique. ISVLSI: International Symposium on Very Large Scale Integration, Jul 2016, Pittsburgh, United States. pp.254-259, ⟨10.1109/ISVLSI.2016.22⟩. ⟨lirmm-01346529⟩
  • Manikandan Palanichamy, Papa-Sidy Ba, Sophie Dupuis, Marie-Lise Flottes, Giorgio Di Natale, et al.. Duplication-based Concurrent Detection of Hardware Trojans in Integrated Circuits. TRUDEVICE, Nov 2016, Barcelona, Spain. ⟨lirmm-01385551⟩
  • Stephan de Castro, Jean-Max Dutertre, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Figure of merits of 28nm Si technologies for implementing laser attack resistant security dedicated circuits. ISVLSI: International Symposium on Very Large Scale Integration, Jul 2015, Montpellier, France. pp.362-367, ⟨10.1109/ISVLSI.2015.76⟩. ⟨emse-01227138⟩
  • Sophie Dupuis, Bruno Rouzeyre, Marie-Lise Flottes, Giorgio Di Natale, Papa-Sidy Ba. New Testing Procedure for Finding Insertion Sites of Stealthy Hardware Trojans. DATE: Design, Automation and Test in Europe, Mar 2015, Grenoble, France. pp.776-781, ⟨10.7873/DATE.2015.1102⟩. ⟨lirmm-01141619⟩
  • Mafalda Cortez, Said Hamdioui, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Hierarchical Secure DfT. TRUDEVICE Workshop, Sep 2015, St Malo, France. ⟨lirmm-01234095⟩
  • Stephan de Castro, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Sensitivity to fault laser injection: a comparison between 28nm bulk and FD-SOI technology. TRUDEVICE Workshop, Sep 2015, Saint-Malo, France. ⟨lirmm-01234094⟩
  • Marie-Lise Flottes, Sophie Dupuis, Papa-Sidy Ba, Bruno Rouzeyre. On the limitations of logic testing for detecting Hardware Trojans Horses. DTIS: Design and Technology of Integrated Systems in Nanoscale Era, Apr 2015, Naples, Italy. ⟨10.1109/DTIS.2015.7127362⟩. ⟨lirmm-01257837⟩
  • Mafalda Cortez, Said Hamdioui, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, et al.. Multi-segment Enhanced Scan-chains for Secure ICs. TRUDEVICE Workshop, Sep 2015, Saint-Malo, France. ⟨lirmm-01276304⟩
  • Marie-Lise Flottes, João Azevedo, Giorgio Di Natale, Bruno Rouzeyre. Session-less based thermal-aware 3D-SIC test scheduling. ETS: European Test Symposium, May 2015, Cluj-Napoca, Romania. ⟨10.1109/ETS.2015.7138732⟩. ⟨lirmm-01922990⟩
  • Papa-Sidy Ba, Manikandan Palanichamy, Sophie Dupuis, Marie-Lise Flottes, Giorgio Di Natale, et al.. Hardware Trojan Prevention using Layout-Level Design Approach. ECCTD: European Conference on Circuit Theory and Design, Aug 2015, Trondheim, Norway. ⟨10.1109/ECCTD.2015.7300093⟩. ⟨lirmm-01234072⟩
  • Yassine Fkih, Pascal Vivet, Marie-Lise Flottes, Bruno Rouzeyre, Giorgio Di Natale, et al.. 3D DFT Challenges and Solutions. ISVLSI: International Symposium on Very Large Scale Integration, Jul 2015, Montpellier, France. pp.603-608, ⟨10.1109/ISVLSI.2015.11⟩. ⟨lirmm-01234076⟩
  • Raphael Andreoni Camponogara-Viera, Rodrigo Possamai Bastos, Jean-Max Dutertre, Olivier Potin, Marie-Lise Flottes, et al.. Validation Of Single BBICS Architecture In Detecting Multiple Faults. ATS: Asian Test Symposium, Nov 2015, Mumbai, India. ⟨lirmm-01234067⟩
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Hakim Zimouche. Built-In Self-Test for Manufacturing TSV Defects before bonding. VTS: VLSI Test Symposium, Apr 2014, Napa, CA, United States. ⟨10.1109/VTS.2014.6818771⟩. ⟨lirmm-00989682⟩
  • Feng Lu, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Layout-Aware Laser Fault Injection Simulation and Modeling: from physical level to gate level. DTIS: Design and Technology of Integrated Systems in Nanoscale Era, May 2014, Santorin, Greece. ⟨10.1109/DTIS.2014.6850665⟩. ⟨lirmm-01119592⟩
  • Yassine Fkih, Pascal Vivet, Bruno Rouzeyre, Marie-Lise Flottes, Giorgio Di Natale, et al.. 2D to 3D Test Pattern Retargeting Using IEEE P1687 Based 3D DFT Architectures. ISVLSI: International Symposium on Very Large Scale Integration, Jul 2014, Tampa, FL, United States. pp.386-391, ⟨10.1109/ISVLSI.2014.83⟩. ⟨lirmm-01119605⟩
  • Feng Lu, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Simulating Laser Effects on ICs, from Physical Level to Gate Level: a comprehensive approach. TRUDEVICE Workshop, May 2014, Paderborn, Germany. ⟨lirmm-01119614⟩
  • Feng Lu, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Customized Cell Detector for Laser-Induced-Fault Detection. IOLTS: International On-Line Testing Symposium, Jul 2014, Platja d'Aro, Spain. pp.37-42, ⟨10.1109/IOLTS.2014.6873669⟩. ⟨lirmm-01119576⟩
  • Sophie Dupuis, Papa-Sidy Ba, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. A Novel Hardware Logic Encryption Technique for thwarting Illegal Overproduction and Hardware Trojans. IOLTS: International On-Line Testing Symposium, Jul 2014, Platja d'Aro, Girona, Spain. pp.49-54, ⟨10.1109/IOLTS.2014.6873671⟩. ⟨lirmm-01025275⟩
  • Vincent Beroulle, Philippe Candelier, Stephan de Castro, Giorgio Di Natale, Jean-Max Dutertre, et al.. Laser-Induced Fault Effects in Security-Dedicated Circuits. VLSI-SoC: Very Large Scale Integration and System-on-Chip, Oct 2014, Playa del Carmen, Mexico. pp.220-240, ⟨10.1007/978-3-319-25279-7_12⟩. ⟨hal-01383737⟩
  • Jean-Max Dutertre, Stephan de Castro, Alexandre Sarafianos, Noémie Boher, Bruno Rouzeyre, et al.. Laser attacks on integrated circuits: from CMOS to FD-SOI. DTIS: Design and Technology of Integrated Systems in Nanoscale Era, May 2014, Santorin, Greece. ⟨10.1109/DTIS.2014.6850664⟩. ⟨emse-01099042⟩
  • Yassine Fkih, Pascal Vivet, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. A 3D IC BIST for pre-bond test of TSVs using Ring Oscillators. NEWCAS: New Circuits and Systems, Jun 2013, Paris, France. pp.001-004. ⟨lirmm-00838524⟩
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Hakim Zimouche. TSVs Pre-Bond Testing: a test scheme for capturing BIST responses. 3D-Test: Testing Three-Dimensional Stacked Integrated Circuits, Sep 2013, Anaheim, CA, United States. ⟨lirmm-00989707⟩
  • Yassine Fkih, Pascal Vivet, Bruno Rouzeyre, Marie-Lise Flottes, Giorgio Di Natale, et al.. 3D Design For Test Architectures Based on IEEE P1687. 3D-Test: Testing Three-Dimensional Stacked Integrated Circuits, Sep 2013, Anaheim, CA, United States. ⟨lirmm-00989717⟩
  • Hakim Zimouche, Marie-Lise Flottes, Bruno Rouzeyre, Giorgio Di Natale. A BIST Method for TSVs Pre-Bond Test. IDT'13: 8th IEEE International Design & Test Symposium, Dec 2013, Marrakesh, Morocco. pp.1-6, ⟨10.1109/IDT.2013.6727081⟩. ⟨lirmm-00989727⟩
  • Sophie Dupuis, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Identification of Hardware Trojans triggering signals. First Workshop on Trustworthy Manufacturing and Utilization of Secure Devices, May 2013, Avignon, France. ⟨lirmm-00991360⟩
  • Jean da Rolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. A smart test controller for scan chains in secure circuits. IOLTS: International On-Line Testing Symposium, Jul 2013, Chania, Greece. pp.228-229, ⟨10.1109/IOLTS.2013.6604085⟩. ⟨lirmm-01430814⟩
  • Feng Lu, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Laser-Induced Fault Simulation. EUROMICRO DSD/SEAA, Sep 2013, Santander, Spain. pp.609-614, ⟨10.1109/DSD.2013.72⟩. ⟨lirmm-01430807⟩
  • Rodrigo Possamai Bastos, Franck Sill Torres, Jean Max Dutertre, Marie-Lise Flottes, Giorgio Di Natale, et al.. A Bulk Built-in Sensor for Detection of Fault Attacks. HOST: Hardware-Oriented Security and Trust, Jun 2013, Austin, TX, United States. pp.51-54, ⟨10.1109/HST.2013.6581565⟩. ⟨lirmm-01430800⟩
  • Jean-Max Dutertre, Rodrigo Possamai Bastos, Olivier Potin, Marie-Lise Flottes, Bruno Rouzeyre, et al.. Sensitivity tuning of a bulk built-in current sensor for optimal transient-fault detection. ESREF: European Symposium on Reliability of Electron devices, Failure physics and analysis, Sep 2013, Arcachon, France. pp.B3c-2 #68. ⟨hal-00872705⟩
  • Rodrigo Possamai Bastos, Frank Sill Torres, Jean-Max Dutertre, Marie-Lise Flottes, Giorgio Di Natale, et al.. A single built-in sensor to check pull-up and pull-down CMOS networks against transient faults. PATMOS: Power and Timing Modeling, Optimization and Simulation, Sep 2013, Karlsruhe, Germany. pp.157-163, ⟨10.1109/PATMOS.2013.6662169⟩. ⟨lirmm-00968621⟩
  • Rodrigo Possamai Bastos, Frank Sill Torres, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Novel transient-fault detection circuit featuring enhanced bulk built-in current sensor with low-power sleep-mode. ESREF: European Symposium on Reliability of Electron devices, Failure physics and analysis, Oct 2012, Cagliari, Italy. ⟨hal-00867864⟩
  • Jean da Rolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. On-Chip Comparison for Testing Secure ICs. DCIS'2012: Conference on Design of Circuits and Integrated Systems, Nov 2012, Avignon, France. pp.112-117. ⟨lirmm-00795205⟩
  • Jean da Rolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Are Advanced DfT Structures Sufficient for Preventing Scan-Attacks?. VTS'12: 30th IEEE VLSI Test Symposium, Apr 2012, Maui, Hawai, United States. pp.246-251. ⟨lirmm-00694536⟩
  • Jean da Rolt, Bruno Rouzeyre, Marie-Lise Flottes, Giorgio Di Natale, Amitabh Das, et al.. A Scan-based Attack on Elliptic Curve Cryptosystems in presence of Industrial Design-for-Testability Structures. IEEE International Symposium on Defect and Fault Tolerance in VLSI & Nanotechnology Systems, United States. http://www.dfts.org/. ⟨lirmm-00744472⟩
  • Jean da Rolt, Amitabh Das, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, et al.. A New Scan Attack on RSA in Presence of Industrial Countermeasures. COSADE: Constructive Side-Channel Analysis and Secure Design, May 2012, Darmstadt, Germany. pp.89-104, ⟨10.1007/978-3-642-29912-4_8⟩. ⟨lirmm-00719986⟩
  • Giorgio Di Natale, Sophie Dupuis, Bruno Rouzeyre. Is Side-Channel Analysis really reliable for detecting Hardware Trojans?. DCIS: Design of Circuits and Integrated Systems, Nov 2012, Avignon, France. pp.238-242. ⟨lirmm-00823477⟩
  • Jean da Rolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. New Security Threats Against Chips Containing Scan Chain Structures. HOST'11: IEEE International Symposium on Hardware-Oriented Security and Trust, San Diego, CA, United States. pp.105-110. ⟨lirmm-00599690⟩
  • Rodrigo Possamai Bastos, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Timing Issues for an Efficient Use of Concurrent Error Detection Codes. LATW: Latin American Test Workshop, Mar 2011, Porto de Galinhas, Brazil. pp.1-6, ⟨10.1109/LATW.2011.5985933⟩. ⟨lirmm-00627427⟩
  • Jean da Rolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Scan Attacks and Countermeasures in Presence of Scan Response Compactors. ETS: European Test Symposium, May 2011, Trondheim, Norway. pp.19-24, ⟨10.1109/ETS.2011.30⟩. ⟨lirmm-00647062⟩
  • Rodrigo Possamai Bastos, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. How to Sample Results of Concurrent Error Detection Schemes in Transient Fault Scenarios?. RADECS: Radiation and Its Effects on Components and Systems, Sep 2011, Sevilla, Spain. pp.635-642, ⟨10.1109/RADECS.2011.6131361⟩. ⟨lirmm-00701776⟩
  • Rodrigo Possamai Bastos, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. A New Bulk Built-in Current Sensor-Based Strategy for Dealing with Long-Duration Transient Faults in Deep-Submicron Technologies. DFT'2011: International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Oct 2011, Vancouver, Canada. pp.302-308, ⟨10.1109/DFT.2011.15⟩. ⟨lirmm-00701789⟩
  • Jean da Rolt, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre. New side-channel attack against scan chains. 9th CryptArchi Workshop (2011), Jun 2011, Bochum, Germany. pp.2. ⟨lirmm-00648575⟩
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Miroslav Valka, Denis Real. Power Consumption Traces Realignment to Improve Differential Power Analysis. DDECS'11: 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits ans Systems, Germany. pp.201-206. ⟨lirmm-00592005⟩
  • Jérôme Di Battista, Jc Courrège, Bruno Rouzeyre, Lionel Torres, Philippe Perdu. When Failure Analysis Meets Side-Channel Attacks. CHES'10: Cryptographic Hardware and Embedded System, Aug 2010, Santa Barbara, United States. pp.188-202, ⟨10.1007/978-3-642-15031-9⟩. ⟨lirmm-00532636⟩
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Evaluation of Resistance to Differential Power Analysis: Execution Time Optimizations for Designers. DELTA'10: Fifth IEEE International Symposium on Electronic Design, Test and Application, Jan 2010, Ho Chi Minh City, Vietnam. pp.256-261. ⟨lirmm-00539993⟩
  • Kaouthar Bousselam, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Evaluation of Concurrent Error Detection Techniques on the Advanced Encryption Standard. IOLTS: International On-Line Testing Symposium, Jul 2010, Corfu, Greece. pp.223-228, ⟨10.1109/IOLTS.2010.5560196⟩. ⟨lirmm-00539232⟩
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Miroslav Valka. Waveforms re-Alignment to Improve DPA Attacks. CryptArchi: Cryptographic Architectures, Jun 2010, Gif-sur-Yvette, France. ⟨lirmm-00539994⟩
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Ensuring High Testability without Degrading Security. DDECS'10: IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, Vienna, Austria. pp.6. ⟨lirmm-00480710⟩
  • Kaouthar Bousselam, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Evaluation of Concurrent Error Detection Techniques on the Advanced Encryption Standard. ETS: European Test Symposium, May 2010, Prague, Czech Republic. ⟨lirmm-00493247⟩
  • Jérôme Di Battista, Philippe Perdu, Jc Courrège, Bruno Rouzeyre, Lionel Torres. Side-Channel Improvment by Laser Stimulation. CryptArchi: Cryptographic Architectures, Jun 2010, Gif-sur-Yvette, France. ⟨lirmm-00575124⟩
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Execution Time Reduction of Differential Power Analysis Experiments. LATW'09: 10th Latin-American Test Workshop, Mar 2009, Armaçao dos Buzios, Brazil, pp.1-5, ⟨10.1109/LATW.2009.4813819⟩. ⟨lirmm-00367712⟩
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Tutorial on Design For Testability & Digital Security. IEEE 10th Latin American Test Workshop, 2009, Buzios, Brazil. ⟨lirmm-00407161⟩
  • Marie-Lise Flottes, Giorgio Di Natale, Paolo Maistri, Bruno Rouzeyre, Régis Leveugle. Ensuring High Testability without Degrading Security. ETS: European Test Symposium, May 2009, Seville, Spain. ⟨lirmm-00407163⟩
  • Jérôme Di Battista, Philippe Perdu, Jc Courrège, Bruno Rouzeyre, Lionel Torres. Validation of Differential Light Emission Analysis on FPGA. SCS'09: International Conference on Signals, Circuits, Systems, Nov 2009, Djerba, Tunisia. ⟨lirmm-00433563⟩
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. An Integrated Validation Environment for Differential Power Analysis. SAME'08: Sophia-Antipolis Forum on MicroElectronics 2008, Sep 2008, Sophia-Antipolis, France. ⟨lirmm-00363796⟩
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. A Reliable Architecture for Substitution Boxes in Integrated Cryptographic. DCIS'08: Conference on Design of Circuits and Integrated Systems, Nov 2008, pp.27-32. ⟨lirmm-00363783⟩
  • Marion Doulcier, Marie-Lise Flottes, Bruno Rouzeyre. AES-based BIST: Self-test, Test Pattern Generation and Signature Analysis. DELTA'08: 4th IEEE International Symposium on Electronic Design, Test & Applications, Jan 2008, Hong-Kong, pp.314-321. ⟨lirmm-00258769⟩
  • Giorgio Di Natale, Marion Doulcier, Marie-Lise Flottes, Bruno Rouzeyre. A Reliable Architecture for the Advanced Encryption Standard. ETS: European Test Symposium, May 2008, Verbania, Italy. pp.13-18. ⟨lirmm-00285868⟩
  • Erika Cota, Julien Dalmasso, Marie-Lise Flottes, Bruno Rouzeyre. Improving the Test of NoC-Based SoCs with Help of Compression Schemes. ISVLSI: IEEE Symposium on Very Large Scale Integration, Apr 2008, Montpellier, France. pp.139-144, ⟨10.1109/ISVLSI.2008.86⟩. ⟨lirmm-00271574⟩
  • Giorgio Di Natale, Marion Doulcier, Marie-Lise Flottes, Bruno Rouzeyre. Low Cost Self-Test of Crypto-Devices. WDSN'08: 2nd Workshop on Dependable and Secure Nanocomputing, Jun 2008, Anchorage, Canada, United States. pp.41-46. ⟨lirmm-00295108⟩
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Observability of Stuck-at-Faults with Differential Power Analysis. LATW'08: IEEE Latin American Test Workshop, Feb 2008, Mexico. pp.N/A. ⟨lirmm-00295498⟩
  • Marie-Lise Flottes, Jean Pouget, Bruno Rouzeyre. Power-Constrained Test Scheduling for SoCs Under a "No Session" Scheme. SoC Design Methodologies, Montpellier, France, pp.401-412. ⟨lirmm-00268504⟩
  • Z. Zeng, M. Ciesielski, Bruno Rouzeyre. Functional Test Generation Using Constraint Logic Programming. SoC Design Methodologies - International Conference on Very Large Scale Integration of Systems-on-Chip, Montpellier, France, pp.375-386. ⟨lirmm-00268536⟩
  • Marie-Lise Flottes, Régis Poirier, Bruno Rouzeyre. A Simple and Effective Compression Scheme for Test Pins Reduction. HLDVT'02: IEEE International Workshop on High Level Design Validation and Test, Cannes (France), France. pp. 165-168. ⟨lirmm-00269326⟩
  • Solaiman Rahim, Jerome Rampon, Bruno Rouzeyre, Lionel Torres. Low Problem in Sequential Equivalence Checking. SAME'02: Sophia-Antipolis Forum on MicroElectronics, Sophia-Antipolis (France), France. pp. 52-57. ⟨lirmm-00269332⟩
  • Solaiman Rahim, Bruno Rouzeyre, Lionel Torres, Jerome Rampon. Matching in the Presence of don't Cares and Redundant Sequential Elements for Sequential Equivalence Checking. HLDVT'03: High Level Design Validation and Test Workshop, San Francisco (USA), France. pp. 129-135. ⟨lirmm-00269707⟩
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Stuck-at-Faults Test using Differential Power Analysis. LPonTR'08: Workshop on Low Power Design Impact on Test and Reliability, May 2008, Italy. ⟨lirmm-00332529⟩
  • Marion Doulcier, Marie-Lise Flottes, Bruno Rouzeyre. L'auto-test d'un coeur de chiffrement AES. JNRDM'08 : Journées Nationales du Réseau Doctoral en Microélectronique, May 2008, France. pp.4. ⟨lirmm-00325878⟩
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. An Integrated Validation Environment for Differential Power Analysis. DELTA: Electronic Design, Test and Applications, Jan 2008, Hong Kong, China. pp.527-532, ⟨10.1109/DELTA.2008.61⟩. ⟨lirmm-00407165⟩
  • Julien Dalmasso, Marie-Lise Flottes, Bruno Rouzeyre. Test Data Compression and TAM Design. IFIP VLSI-SOC 2007 - IFIP WG 10.5 International Conference on Very Large Scale Integration, Oct 2007, Atlanta, GA, USA, pp.178-183. ⟨lirmm-00186171⟩
  • Marion Doulcier, Marie-Lise Flottes, Bruno Rouzeyre. AES vs LFSR Based Test Pattern Generation: A Comparative Study. LATW: Latin American Test Workshop, Mar 2007, Cuzco, Peru. pp.314-321. ⟨lirmm-00138831⟩
  • Marie-Lise Flottes, Marion Doulcier, Bruno Rouzeyre. Utilisation de ressources cryptographiques pour le test des circuits sécurisés. Colloque du GDR SoC-SiP, Jun 2007, Paris, France. ⟨lirmm-00203332⟩
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. An On-Line Fault Detection Scheme for SBoxes in Secure Circuits. IOLTS: International On-Line Testing Symposium, Jul 2007, Heraklion, Crete, Greece. pp.57-62, ⟨10.1109/IOLTS.2007.16⟩. ⟨lirmm-00163244⟩
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. A Novel Parity Bit Scheme for SBOX in AES Circuits. DDECS'07: Design and Diagnostics of Electronic Cicruits and Systems, Apr 2007, Cracovie, Pologne, pp.267-271. ⟨lirmm-00141799⟩
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. On-Line Self-Test of AES Hardware Implementations. DSN'07: Workshop on Dependable and Secure Nanocomputing, Jun 2007, Edinburgh, United Kingdom. ⟨lirmm-00163405⟩
  • Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre, Marion Doulcier. Test and Security. CryptArchi: Cryptographic Architectures, Jun 2007, Montpellier, France. ⟨lirmm-00163017⟩
  • Julien Dalmasso, Marie-Lise Flottes, Bruno Rouzeyre. Fitting ATE Channels with Scan Chains: A Comparison Between a Test Data Compression Technique and Serial Loading of Scan Chains. DELTA'06: Third IEEE International Workshop on Electronics DesignTest & Applications, Kuala Lumpur (Malaysia), pp.295-300. ⟨lirmm-00102704⟩
  • David Hely, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre. Scan Pattern Watermarking. LATW'06: 7th IEEE Latin American Test Workshop, Mar 2006, Buenos Aires, pp.63-67. ⟨lirmm-00102753⟩
  • Julien Dalmasso, Marie-Lise Flottes, Bruno Rouzeyre. Compression de Données de Test : Réduction du Nombre de Broches et Gain en Temps de Test. JNRDM: Journées Nationales du Réseau Doctoral de Microélectronique, May 2006, Rennes, France. ⟨lirmm-00102830⟩
  • David Hély, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre. A Secure Scan Design Methodology. LATW'06: 7th IEEE Latin American Test Workshop, Mar 2006, Buenos Aires, Argentina. pp.81-86. ⟨lirmm-00102752⟩
  • David Hély, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre. Secure Scan Techniques: a Comparison. IOLTS: International On-Line Testing Symposium, Jul 2006, Como, Italy. pp.119-124, ⟨10.1109/IOLTS.2006.55⟩. ⟨lirmm-00102857⟩
  • David Hély, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre. A secure Scan Design Methodology. DATE: Design, Automation and Test in Europe, Mar 2006, Munich, Germany. pp.1177-1178, ⟨10.1109/DATE.2006.244019⟩. ⟨lirmm-00132516⟩
  • Mathieu Scholivé, Vincent Beroulle, Chantal Robach, Marie-Lise Flottes, Bruno Rouzeyre. Mutation Sampling Technique for the Generation of Structural Test Data. DATE: Design, Automation and Test in Europe, 2005, Munich, Germany. pp.1022. ⟨lirmm-00105978⟩
  • David Hely, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre. Test Control for Secure Scan Designs. ETS: European Test Symposium, May 2005, Tallinn, Estonia. pp.190-195. ⟨lirmm-00106011⟩
  • David Hely, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre. Scan Design and Secure Chips : Can They Work Together. SAME'05: Sophia-Antipolis Forum on MicroElectronics, Oct 2005, Sophia-Antipolis, France. ⟨lirmm-00106546⟩
  • Mathieu Scholivé, Vincent Beroulle, Chantal Robach, Marie-Lise Flottes, Bruno Rouzeyre. Mutation sampling technique for the generation of structural test data. 6th IEEE Latin American Test Workshop, Mar 2005, Salvador, Bahia, Brazil. ⟨hal-00378490⟩
  • Mathieu Scholivé, Vincent Beroulle, Chantal Robach, Marie-Lise Flottes, Bruno Rouzeyre. Mutation Sampling Technique for the Generation of Structural Test Data. DATE: Design, Automation and Test in Europe, Mar 2005, Munich, Germany. pp.1022-1023. ⟨hal-00181680⟩
  • Solaiman Rahim, Jerome Rampon, Bruno Rouzeyre, Lionel Torres. An Efficient Flip-Flops Matching Engine. DDECS'04: 7th IEEE International Workshop on Design and Diagnostics of Electronic Circuits and Systems, Apr 2004, Slovakia, pp.105-113. ⟨lirmm-00108773⟩
  • Marie-Lise Flottes, Régis Poirier, Bruno Rouzeyre. On Using Test Vector Differences for Reducing Test Pin Numbers. DELTA'04: 2nd International Workshop on Electronic DesignTest and Applications, Jan 2004, Perth (Australia), pp.275-280. ⟨lirmm-00108832⟩
  • L. Krundel, S. Kumar Goel, E.J. Marinissen, Marie-Lise Flottes, Bruno Rouzeyre. User-Constrained Test Architecture Design for Modular SOC Testing. ETS: European Test Symposium, May 2004, Ajaccio, Corsica, France. pp.80-85, ⟨10.1109/ETSYM.2004.1347611⟩. ⟨lirmm-00108903⟩
  • David Hely, Marie-Lise Flottes, Frédéric Bancel, Bruno Rouzeyre, Nicolas Berard, et al.. Scan design and secure chip [secure IC testing]. IOLTS: International On-Line Testing Symposium, Jul 2004, Madeira Island, Portugal. pp.219-224, ⟨10.1109/OLT.2004.1319691⟩. ⟨lirmm-00108909⟩
  • Marie-Lise Flottes, Régis Poirier, Bruno Rouzeyre. An Arithmetic Structure for Test Data Horizontal Compression. DATE: Design, Automation and Test in Europe, Feb 2004, Paris, France. pp.428-434, ⟨10.1109/DATE.2004.1268884⟩. ⟨lirmm-00108837⟩
  • Solaiman Rahim, Bruno Rouzeyre, Lionel Torres, Jerome Rampon. Matching in the Presence of don't Cares and Redundant Sequential Elements for Sequential Equivalence Checking. HLDVT'03: High Level Design Validation and Test Workshop, San Francisco, United States. pp.129-135. ⟨lirmm-00269474⟩
  • Mathieu Scholivé, Vincent Beroulle, Chantal Robach, Marie-Lise Flottes, Bruno Rouzeyre. Software-Based Testing of Sequential VHDL Descriptions. ETW: European Test Workshop, Mar 2003, Maastricht, Netherlands. pp.199-200. ⟨lirmm-00269437⟩
  • Julien Pouget, Erik Larsson, Zebo Peng, Marie-Lise Flottes, Bruno Rouzeyre. An Efficient Approach to SoC Wrapper Design, TAM Configuration and Test Scheduling. ETW: European Test Workshop, 2003, Maastricht, Netherlands. pp.51-56. ⟨lirmm-00191948⟩
  • Solaiman Rahim, Bruno Rouzeyre, Lionel Torres, Jerome Rampon. Matching in the Presence of don't Cares and Redundant Sequential Elements for Sequential Equivalence Checking. HLDVT'03: High Level Design Validation and Test Workshop, San Francisco (USA), France. pp. 129-135. ⟨lirmm-00191957⟩
  • Marie-Lise Flottes, Julien Pouget, Bruno Rouzeyre. A Heuristic for Test scheduling at System Level. DATE: Design, Automation and Test in Europe, Mar 2002, Paris, France. pp.1124-1124, ⟨10.1109/DATE.2002.998480⟩. ⟨lirmm-00268503⟩
  • Maciej Ciesielski, Priyank Kalla, Zhihong Zheng, Bruno Rouzeyre. Taylor Expansion Diagrams: A Compact, Canonical Representation with Applications to Symbolic Verification. DATE: Design, Automation and Test in Europe, Mar 2002, Paris, France. pp.285-289, ⟨10.1109/DATE.2002.998286⟩. ⟨lirmm-00268497⟩
  • Christian Landrault, Marie-Lise Flottes, Bruno Rouzeyre. Is high level test synthesis just design for test?. ITC: International Test Conference, Oct 1995, Washington, DC, United States. pp.294-298, ⟨10.1109/TEST.1995.529846⟩. ⟨lirmm-02288898⟩
  • F. Monteiro, Bruno Rouzeyre, Georges Sagnes. High level synthesis: a data path partitioning method dedicated to speed enhancement. EDAC: European Conference on Design Automation, Feb 1991, Amsterdam, Netherlands. pp.123-128, ⟨10.1109/EDAC.1991.206374⟩. ⟨lirmm-02288876⟩

Poster communications16 documents

  • Emanuele Valea, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre. Encryption Techniques for Test Infrastructures. Colloque du GDR SoC-SiP, Jun 2019, Montpellier, France. 13ème Colloque National du GDR SOC2. ⟨lirmm-02306922⟩
  • Mathieu da Silva, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Scan chain encryption, a countermeasure against scan attacks. PHISIC: Practical Hardware Innovations in Security Implementation and Characterization, May 2018, Gardanne, France. Workshop on Practical Hardware Innovations in Security Implementation and Characterization, 2018. ⟨lirmm-01882565v2⟩
  • Mathieu da Silva, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre. Sécurité des moyens de test des SoC. Journée thématique des GDR SoC² et Sécurité Informatique : Sécurité des SoC complexes hétérogènes – de la TEE au matériel, Sep 2018, Paris, France. 2018. ⟨lirmm-01882552⟩
  • Emanuele Valea, Mathieu da Silva, Giorgio Di Natale, Marie-Lise Flottes, Sophie Dupuis, et al.. SECCS: SECure Context Saving for IoT Devices. Colloque du GDR SoC-SiP, Jun 2018, Paris, France. 12ème Colloque National du GDR SoC-SiP, 2018. ⟨hal-02042659⟩
  • Mathieu da Silva, Emanuele Valea, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre. Stream cipher-based scan encryption in test standards. Colloque du GDR SoC-SiP, Jun 2018, Paris, France. 12ème Colloque National du GDR SoC-SiP, 2018. ⟨lirmm-01867283⟩
  • Mathieu da Silva, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Scan chain encryption in Test Standards. SURREALIST: SecURity, REliAbiLity, test, prIvacy, Safety and Trust of Future Devices, May 2018, Bremen, Germany. Workshop on SecURity, REliAbiLity, test, prIvacy, Safety and Trust of Future Devices, 2018. ⟨lirmm-01882578v2⟩
  • Mathieu da Silva, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Scan Chain Encryption for the Test, Diagnosis and Debug of Secure Circuits. SETS: South European Test Seminar, Mar 2017, Alpe d'Huez, France. 2017. ⟨lirmm-01892667⟩
  • Mathieu da Silva, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre. Sécurisation des structures de test : étude comparative. Colloque du GDR SoC-SiP, Jun 2017, Bordeaux, France. 11ème Colloque National du GDR SoC-SiP, 2017. ⟨lirmm-01867279⟩
  • Papa-Sidy Ba, Sophie Dupuis, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre. Detection and Prevention of Hardware Trojan through Logic Testing. TRUDEVICE, Nov 2016, Barcelona, Spain. 4th Workshop on Trustworthy Manufacturing and Utilization of Secure Devices, Manufacturing test of secure devices / Reverse engineering countermeasures / Other topics, pp.#33, 2016, Posters IV. ⟨lirmm-01430007⟩
  • Jean-Max Dutertre, Rodrigo Possamai Bastos, Olivier Potin, Marie-Lise Flottes, Giorgio Di Natale, et al.. Design of Bulk Built-In Current Sensors to Detect Single Event Effects and Laser-Induced Fault Injection Attempts. Joint MEDIAN–TRUDEVICE Open Forum, Sep 2014, Amsterdam, Netherlands. 2014. ⟨emse-01099040⟩
  • Rodrigo Possamai Bastos, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Calibrating Bulk Built-in Current Sensors for Detecting Transient Faults. Colloque GDR SoC-SiP, 2012, Lyon, France. 2012, Colloque National du Groupement de Recherche System-On-Chip et System-In-Package. ⟨lirmm-00715126⟩
  • Giorgio Di Natale, Marie-Lise Flottes, Feng Lu, Bruno Rouzeyre. tLIFTING : A Multi-level Delay-annotated Fault Simulator for Digital Circuits. DCIS'2012: XVII Conference on Design of Circuits and Integrated Systems, Nov 2012, avignon, France. pp.1, 2012. ⟨lirmm-00799892⟩
  • Rodrigo Possamai Bastos, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Timing Issues of Transient Faults in Concurrent Error Detection Schemes. GdR SoC-SiP'2011: Colloque national du Groupement de Recherche System-On-Chip et System-In-Package, Lyon, France. http://www2.lirmm.fr/~w3mic/SOCSIP/, 2011. ⟨lirmm-00701798⟩
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. A Dependable Parallel Architecture for SBoxes. ReCoSoc'07: International Workshop on Reconfigurable Communication Centric System-On-Chips, Jun 2007, Montpellier, France. pp.CD-ROM, 2007. ⟨lirmm-00163414⟩
  • Erika Cota, Julien Dalmasso, Marie-Lise Flottes, Bruno Rouzeyre. Improving NoC-based Testing Through Compression Schemes. DATE: Design, Automation and Test in Europe, Apr 2007, Nice, France. 2007. ⟨lirmm-00170833⟩
  • Julien Dalmasso, Marie-Lise Flottes, Bruno Rouzeyre. TAM Design and Test Data Compression for SoC Test Cost Reduction. ETS: European Test Symposium, May 2007, Freiburg, Germany. 12th IEEE European Test Symposium, pp.241-246, 2007. ⟨lirmm-00159044⟩

Books1 document

  • Florence Azaïs, Serge Bernard, Yves Bertrand, Marie-Lise Flottes, Patrick Girard, et al.. Test de Circuits et de Systèmes Intégrés. Collection EGEM, Ed.Hermès, 2004, 2-7462-0864-4. ⟨lirmm-00109158⟩

Book sections5 documents

  • Kaouthar Bousselam, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Chapitre 6 : On Countermeasures Against Fault Attacks on the Advanced Encryption Standard. Marc Joye and Michael Tunstall. Fault Analysis in Cryptography, Springer, pp.89-109, 2012, Information Security and Cryptography, 978-3-642-29656-0 (-7 for eBook). ⟨lirmm-00744671⟩
  • Kaouthar Bousselam, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Chapter 9: Fault Detection in Crypto-devices. Wei Zhang. Fault Detection, InTech, pp.177-194, 2010, 978-953-307-037-7. ⟨10.5772/213⟩. ⟨lirmm-00437252⟩
  • Julien Dalmasso, Marie-Lise Flottes, Bruno Rouzeyre. Compression-Based SoC Test Infrastructures. VLSI-SoC: Advanced Topics on Systems on a Chip, 291, Springer, pp.53-68, 2009, IFIP Advances in Information and Communication Technology, 978-0-387-89557-4. ⟨lirmm-00375078⟩
  • Eric Senn, Eric Martin, M. Robert, Bruno Rouzeyre, C. Piguet, et al.. A Vision System on Chip for Industrial Contro. International Federation for Information Processing, Springer, 2002. ⟨hal-00083323⟩
  • Christophe Vial, Bruno Rouzeyre. Hardware/Software Co-Synthesis: Modelling and Synthesis of Interfaces Using Interpreted Petri Nets. Hardware/Software Co-Design and Co-Verification, Current Issues in Electronic Modeling (CIEM) (8), Springer, pp.89-107, 1997, 978-1-4419-5159-5. ⟨10.1007/978-1-4757-2629-9_4⟩. ⟨lirmm-02288856⟩

Other publications19 documents

  • Patrick Girard, Serge Bernard, Florence Azaïs, Alberto Bosio, Luigi Dilillo, et al.. Rapport Technique de fin d'année, Contrat TOETS CT 302, Programme CEE CATRENE. 2011. ⟨lirmm-00679022⟩
  • Patrick Girard, Serge Bernard, Florence Azaïs, Alberto Bosio, Luigi Dilillo, et al.. Rapport Technique intermédiaire, Contrat TOETS CT 302, Programme CEE CATRENE. 2011. ⟨lirmm-00679018⟩
  • Patrick Girard, Serge Bernard, Florence Azaïs, Alberto Bosio, Luigi Dilillo, et al.. Contrat TOETS CT 302 - Programme CEE CATRENE (Rapport Intermédiaire). 2010. ⟨lirmm-00504873⟩
  • Patrick Girard, Florence Azaïs, Serge Bernard, Alberto Bosio, Luigi Dilillo, et al.. TOETS CT302 - Programme CEE CATRENE - Summary Technical Report 2S-2009 - Rapport Technique de Fin d'année. 2010. ⟨lirmm-00461745⟩
  • Patrick Girard, Serge Bernard, Alberto Bosio, Luigi Dilillo, Marie-Lise Flottes, et al.. Rapport Technique de fin de Contrat NanoTEST 2A702, Programme CEE MEDEA+. 2009. ⟨lirmm-00406974⟩
  • Marion Doulcier, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Test and Harware Security. 2008. ⟨lirmm-00365276⟩
  • Patrick Girard, Serge Bernard, Alberto Bosio, Marie-Lise Flottes, Serge Pravossoudovitch, et al.. Contrat NanoTEST 2A702 - Programme CEE MEDEA - Rapport Technique intermédiaire. 2007. ⟨lirmm-00199966⟩
  • Patrick Girard, Serge Bernard, Alberto Bosio, Marie-Lise Flottes, Serge Pravossoudovitch, et al.. Contrat NanoTEST 2A702 - Programme CEE MEDEA - Rapport Technique de fin d'année. 2007. ⟨lirmm-00199958⟩
  • Patrick Girard, Serge Bernard, Marie-Lise Flottes, Christian Landrault, Serge Pravossoudovitch, et al.. Contrat NanoTEST 2A702 - Programme CEE MEDEA+. 2006. ⟨lirmm-00102699⟩
  • Patrick Girard, Serge Bernard, Marie-Lise Flottes, Christian Landrault, Serge Pravossoudovitch, et al.. Contrat NanoTEST 2A702, Programme CEE MEDEA +. 2006. ⟨lirmm-00130759⟩
  • Patrick Girard, Serge Bernard, Marie-Lise Flottes, Christian Landrault, Serge Pravossoudovitch, et al.. Contrat NanoTEST 2A702, Programme CEE MEDEA+. 2006. ⟨lirmm-00130758⟩
  • Bruno Rouzeyre, Marie-Lise Flottes. Test Circuits Sécurisés 2. 2004, 2 p. ⟨lirmm-00109182⟩
  • Patrick Girard, Michel Renovell, Serge Bernard, Marie-Lise Flottes, Serge Pravossoudovitch, et al.. Advanced Solutions for Innovative SOC Testing in Europe. 2004. ⟨lirmm-00109190⟩
  • Bruno Rouzeyre, Marie-Lise Flottes. Test Circuits Sécurisés 1. 2003, pp.3. ⟨lirmm-00191973⟩
  • Bruno Rouzeyre, Marie-Lise Flottes. Test Circuits Sécurisés 1. 2003, 3 p. ⟨lirmm-00269490⟩
  • Patrick Girard, Michel Renovell, Florence Azaïs, Yves Bertrand, Marie-Lise Flottes, et al.. Advanced Solutions for Innovative SOC Testing in Europe, Contrat CEE ASSOCIATE A503, Programme MEDEA+ (Rapport Technique Intermédiaire). 2003, pp.P nd. ⟨lirmm-00269720⟩
  • Patrick Girard, Michel Renovell, Florence Azaïs, Serge Bernard, Marie-Lise Flottes, et al.. Advanced Solutions for Innovative SOC Testing in Europe, Contrat CEE ASSOCIATE A503, Programme MEDEA+ (Rapport Technique de Fin d'Année). 2003, pp.P nd. ⟨lirmm-00269749⟩
  • Bruno Rouzeyre, Marie-Lise Flottes. Test Circuits Sécurisés 1. 2003, 3 p. ⟨lirmm-00269804⟩
  • Patrick Girard, Florence Azaïs, Serge Bernard, Yves Bertrand, Marie-Lise Flottes, et al.. Advanced Solutions for Innovative SOC Testing in Europe. 2002. ⟨lirmm-00268586⟩

Reports3 documents

  • Patrick Girard, Serge Bernard, Alberto Bosio, Marie-Lise Flottes, Serge Pravossoudovitch, et al.. Contrat Nano TEST 2A702, Programme CEE MEDEA (Rapport Intermédiaire). 08027, 2008. ⟨lirmm-00344415⟩
  • Patrick Girard, Serge Bernard, Alberto Bosio, Marie-Lise Flottes, Serge Pravossoudovitch, et al.. Contrat Nano TEST 2A702, Programme CEE MEDEA (Rapport Technique de fin d'année). 08026, 2008. ⟨lirmm-00344408⟩
  • Nadia El Mrabet, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Jean-Claude Bajard. Differential Power Analysis against the Miller Algorithm. RR-08021, 2008. ⟨lirmm-00323684⟩