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173

Publications of Bruno Rouzeyre


Article dans une revue21 documents

  • Raphael Andreoni Camponogara-Viera, Jean-Max Dutertre, O. Potin, Marie-Lise Flottes, Giorgio Di Natale, et al.. Assessing Body Built-In Current Sensors for Detection of Multiple Transient Faults. Microelectronics Reliability, Elsevier, 2018. 〈hal-01893676〉
  • Sophie Dupuis, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre. Protection against Hardware Trojans with Logic Testing: Proposed Solutions and Challenges Ahead. IEEE Design & Test, IEEE, 2018, 35 (2), pp.73-90. 〈10.1109/MDAT.2017.2766170〉. 〈lirmm-01688166〉
  • Mathieu Da Silva, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre. Preventing Scan Attacks on Secure Circuits Through Scan Chain Encryption. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE, 2018, 〈10.1109/TCAD.2018.2818722〉. 〈lirmm-01867245〉
  • Stephan De Castro, Jean-Max Dutertre, Bruno Rouzeyre, Giorgio Di Natale, Marie-Lise Flottes. Frontside Versus Backside Laser Injection: A Comparative Study. ACM Journal on Emerging Technologies in Computing Systems, Association for Computing Machinery, 2016, Special Issue on Secure and Trustworthy Computing, 13 (1), pp.Art 7. 〈10.1145/2845999〉. 〈lirmm-01444121〉
  • Jean Da Rolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Thwarting Scan-Based Attacks on Secure-ICs with On-Chip Comparison. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE, 2014, 22 (4), pp.947-951. 〈10.1109/TVLSI.2013.2257903〉. 〈lirmm-00841650〉
  • Jean-Max Dutertre, Rodrigo Possamai Bastos, Olivier Potin, Marie-Lise Flottes, Bruno Rouzeyre, et al.. Improving the ability of Bulk Built-In Current Sensors to detect Single Event Effects by using triple-well CMOS. Microelectronics Reliability, Elsevier, 2014, 54 (9-10), pp.2289-2294. 〈10.1016/j.microrel.2014.07.151〉. 〈emse-01094805〉
  • Sophie Dupuis, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. On the Effectiveness of Hardware Trojan Horse Detection via Side-Channel Analysis. Information Security Journal: A Global Perspective, Taylor & Francis, 2014, Trustworthy Manufacturing and Utilization of Secure Devices, 22 (5-6), pp.226-236. 〈10.1080/19393555.2014.891277〉. 〈lirmm-00991362〉
  • Feng Lu, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Multi-Level Ionizing-Induced Transient Fault Simulator. Information Security Journal: A Global Perspective, Taylor & Francis, 2014, 22 (5-6), pp.251-264. 〈http://www.tandfonline.com/doi/abs/10.1080/19393555.2014.891280#.VEEP7tTLc4l〉. 〈10.1080/19393555.2014.891280〉. 〈lirmm-01075393〉
  • Jean Da Rolt, Amitabh Das, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, et al.. Test versus Security: Past and Present. IEEE Transactions on Emerging Topics in Computing, Institute of Electrical and Electronics Engineers, 2014, pp.13. 〈http://www.computer.org/csdl/trans/ec/preprint/06733305-abs.html〉. 〈10.1109/TETC.2014.2304492〉. 〈lirmm-00989627〉
  • Rodrigo Possamai Bastos, Giorgio Di Natale, Marie-Lise Flottes, Feng Lu, Bruno Rouzeyre. A New Recovery Scheme Against Short-to-Long Duration Transient Faults in Combinational Logic. Journal of Electronic Testing, Springer Verlag, 2013, pp.001-010. 〈10.1007/s10836-013-5359-y〉. 〈lirmm-00838389〉
  • Amitabh Das, Jean Da Rolt, Santosh Ghosh, Stefaan Seys, Sophie Dupuis, et al.. Secure JTAG Implementation Using Schnorr Protocol. Journal of Electronic Testing, Springer Verlag, 2013, 29 (2), pp.193-209. 〈10.1007/s10836-013-5369-9〉. 〈lirmm-00837904〉
  • Jean-Max Dutertre, Rodrigo Possamai Bastos, Olivier Potin, Marie-Lise Flottes, Bruno Rouzeyre, et al.. Sensitivity tuning of a bulk built-in current sensor for optimal transient-fault detection. Microelectronics Reliability, Elsevier, 2013, European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, 53 (9), pp.1320-1324. 〈10.1016/j.microrel.2013.07.069〉. 〈emse-01100723〉
  • Jean Da Rolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. A Novel Differential Scan Attack on Advanced DFT Structures. ACM Transactions on Design Automation of Electronic Systems, Association for Computing Machinery, 2013, 18 (4), pp.58. 〈10.1145/2505014〉. 〈lirmm-01075410〉
  • Rodrigo Possamai Bastos, Frank Sill Torres, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Novel Transient-Fault Detection Circuit Featuring Enhanced Bulk Built-in Current Sensor with Low-Power Sleep Mode. Microelectronics Reliability, Elsevier, 2012, 52 (9-10), pp.1781-1786. 〈10.1016/j.microrel.2012.06.149〉. 〈lirmm-00715117〉
  • Jean Da Rolt, Amitabh Das, Santosh Ghosh, Giorgio Di Natale, Marie-Lise Flottes, et al.. Scan Attacks on Side-channel and Fault Attack Resistant Public-key Implementations. Journal of Cryptographic Engineering, Springer, 2012, 2 (4), pp.207-219. 〈10.1007/s13389-012-0045-z〉. 〈lirmm-01075412〉
  • Jean Da Rolt, Amitabh Das, Santos Ghosh, Giorgio Di Natale, Marie-Lise Flottes, et al.. Scan attacks on side-channel and fault attack resistant public-key implementations. Journal of Cryptographic Engineering, Springer, 2012, 2 (4), pp.207-219. 〈10.1007/s13389-012-0045-z〉. 〈lirmm-00805687〉
  • Giorgio Di Natale, Marion Doulcier, Marie-Lise Flottes, Bruno Rouzeyre. Self-Test Techniques for Crypto-Devices. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE, 2009, 18 (2), pp.329-333. 〈10.1109/TVLSI.2008.2010045〉. 〈lirmm-00365359〉
  • Giorgio Di Natale, Doulcier Marion, Marie-Lise Flottes, Bruno Rouzeyre. A Reliable Architecture for Parallel Implementations of the Advanced Encryption Standard. Journal of Electronic Testing, Springer Verlag, 2009, 25 (4-5), pp.269-278. 〈10.1007/s10836-009-5106-6〉. 〈lirmm-00423026〉
  • David Hely, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre. Securing Scan Control in Crypto Chips. Journal of Electronic Testing, Springer Verlag, 2007, 23 (5), pp.457-464. 〈10.1007/s10836-007-5000-z〉. 〈lirmm-00186353〉
  • Solaiman Rahim, Bruno Rouzeyre, Lionel Torres. A Flip-Flop Matching Engine to Verify Sequential Optimizations. Computing and Informatics, Slovak University Press, Bratislava, 2004, 24 (5-6), pp.437-460. 〈lirmm-00108550〉
  • Marie-Lise Flottes, Bruno Rouzeyre, Leo Volpe. Improving Datapath Testability by Modifying Controller Specification. VLSI Design, Hindawi Publishing Corporation, 2002, 15 (2), pp.491-498. 〈10.1080/1065514021000012101〉. 〈lirmm-00268581〉

Communication dans un congrès113 documents

  • Jean-Max Dutertre, Vincent Beroulle, Philippe Candelier, Louis-Barthelemy Faber, Marie-Lise Flottes, et al.. The case of using CMOS FD-SOI rather than CMOS bulk to harden ICs against laser attacks. IOLTS: International On-Line Testing Symposium, Jul 2018, Platja d’Aro, Spain. 24th IEEE International Symposium on On-Line Testing and Robust System Design, 2018, 〈http://tima.univ-grenoble-alpes.fr/conferences/iolts/iolts18/〉. 〈10.1109/IOLTS.2018.8474230〉. 〈emse-01856000〉
  • Jean-Max Dutertre, Vincent Beroulle, Philippe Candelier, Stephan De Castro, Faber Louis-Barthelemy, et al.. Laser fault injection at the CMOS 28 nm technology node: an analysis of the fault model. FDTC: Fault Diagnosis and Tolerance in Cryptography, Sep 2018, Amsterdam, Netherlands. 14th Workshop on Fault Diagnosis and Tolerance in Cryptography, 2018. 〈emse-01856008〉
  • Mathieu Da Silva, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre. Does stream cipher-based scan chains encryption really prevent scan attacks?. TRUDEVICE Workshop, Mar 2018, Dresden, Germany. Trustworthy Manufacturing and Utilization of Secure Devices, W05, 2018, 〈https://www.date-conference.com/date18/conference/workshop-w05〉. 〈lirmm-01867286〉
  • Mathieu Da Silva, Emanuele Valea, Marie-Lise Flottes, Sophie Dupuis, Giorgio Di Natale, et al.. Encryption of test data: which cipher is better?. PRIME: PhD Research in Microelectronics and Electronics, Jul 2018, Prague, Czech Republic. IEEE, 14th Conference on PhD Research in Microelectronics and Electronics, 2018, 〈http://www.prime2018.org〉. 〈10.1109/PRIME.2018.8430366〉. 〈lirmm-01867249〉
  • Mathieu Da Silva, Emanuele Valea, Marie-Lise Flottes, Sophie Dupuis, Giorgio Di Natale, et al.. A new secure stream cipher for scan chain encryption. IVSW: International Verification and Security Workshop, Jul 2018, Platja d’Aro, Spain. 3nd International Verification and Security Workshop, 2018, 〈http://tima.univ-grenoble-alpes.fr/conferences/ivsw/ivsw18/〉. 〈lirmm-01867256〉
  • Mathieu Da Silva, Emanuele Valea, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre. Stream cipher-based scan encryption in test standards. Colloque GDR SoC2, 2018, Paris, France. 2018. 〈lirmm-01867283〉
  • Emanuele Valea, Mathieu Da Silva, Giorgio Di Natale, Marie-Lise Flottes, Sophie Dupuis, et al.. SECCS: SECure Context Saving for IoT Devices. DTIS: Design and Technology of Integrated Systems in Nanoscale Era, Apr 2018, Taormina, Italy. 13th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2018, 〈www.lirmm.fr/DTIS18/〉. 〈hal-01740173〉
  • Giorgio Di Natale, Marie-Lise Flottes, Sophie Dupuis, Bruno Rouzeyre. Hacking the Control Flow error detection mechanism. IVSW: International Verification and Security Workshop, Jul 2017, Thessaloniki, Greece. IEEE, 2nd IEEE International Verification and Security Workshop, 2017, 〈http://tima.univ-grenoble-alpes.fr/conferences/ivsw/ivsw17/〉. 〈10.1109/IVSW.2017.8031544〉. 〈lirmm-01700739〉
  • Mathieu Da Silva, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre. Scan Chain Encryption. DOCTIS: Journée des Doctorants de l’école doctorale I2S, 2017, Montpellier, France. 2017. 〈lirmm-01867277〉
  • Mathieu Da Silva, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre. Sécurisation des structures de test : étude comparative. Colloque GDR SoC2, 2017, Bordeaux, France. 2017. 〈lirmm-01867279〉
  • Mathieu Da Silva, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre, Paolo Prinetto, et al.. Scan chain encryption for the test, diagnosis and debug of secure circuits. ETS: European Test Symposium, May 2017, Limassol, Cyprus. IEEE, 22nd IEEE European Test Symposium, 2017, 〈10.1109/ETS.2017.7968248〉. 〈lirmm-01699254〉
  • Mathieu Da Silva, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre. Experimentations on scan chain encryption with PRESENT. IVSW: International Verification and Security Workshop, Jul 2017, Thessaloniki, Greece. IEEE, 2nd IEEE International Verification and Security Workshop, 2017, 〈http://tima.imag.fr/conferences/ivsw/ivsw17/〉. 〈10.1109/IVSW.2017.8031543〉. 〈lirmm-01699258〉
  • Papa-Sidy Ba, Sophie Dupuis, Manikandan Palanichamy, Marie-Lise Flottes, Giorgio Di Natale, et al.. Hardware Trust through Layout Filling: a Hardware Trojan Prevention Technique. ISVLSI: IEEE Computer Society Annual Symposium on VLSI, Jul 2016, Pittsburgh, United States. 2016, 〈http://www.isvlsi.org〉. 〈10.1109/ISVLSI.2016.22〉. 〈lirmm-01346529〉
  • Papa-Sidy Ba, Sophie Dupuis, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre. Using Outliers to Detect Stealthy Hardware Trojan Triggering?. IVSW: International Verification and Security Workshop, Jul 2016, Sant Feliu de Guixols, France. IEEE International Verification and Security Workshop, 2016. 〈lirmm-01347119〉
  • Manikandan Palanichamy, Papa-Sidy Ba, Sophie Dupuis, Marie-Lise Flottes, Giorgio Di Natale, et al.. Duplication-based Concurrent Detection of Hardware Trojans in Integrated Circuits. TRUDEVICE, Nov 2016, Barcelona, Spain. 5th Workshop on Trustworthy Manufacturing and Utilization of Secure Devices, 2016, 〈https://trudevice2016.eel.upc.edu/〉. 〈lirmm-01385551〉
  • Mafalda Cortez, Said Hamdioui, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Hierarchical Secure DfT. TRUDEVICE Workshop, Sep 2015, St Malo, France. 4th Workshop on Secure Hardware and Security Evaluation, 2015. 〈lirmm-01234095〉
  • Mafalda Cortez, Said Hamdioui, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, et al.. Multi-segment Enhanced Scan-chains for Secure ICs. TRUDEVICE Workshop, Sep 2015, Saint-Malo, France. 4th Workshop on Secure Hardware and Security Evaluation, 2015. 〈lirmm-01276304〉
  • Stephan De Castro, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Sensitivity to fault laser injection: a comparison between 28nm bulk and FD-SOI technology. TRUDEVICE Workshop, Sep 2015, Saint-Malo, France. 2015. 〈lirmm-01234094〉
  • Papa-Sidy Ba, Palanichamy Manikandan, Sophie Dupuis, Marie-Lise Flottes, Giorgio Di Natale, et al.. Hardware Trojan Prevention using Layout-Level Design Approach. IEEE. ECCTD: European Conference on Circuit Theory and Design, Aug 2015, Trondheim, Norway. Proceedings of the 2015 European Conference on Circuit Theory and Design (ECCTD), 〈10.1109/ECCTD.2015.7300093〉. 〈lirmm-01234072〉
  • Yassine Fkih, Pascal Vivet, Marie-Lise Flottes, Bruno Rouzeyre, Giorgio Di Natale, et al.. 3D DFT Challenges and Solutions. ISVLSI: IEEE Computer Society Annual Symposium on VLSI, Jul 2015, Montpellier, France. pp.603-608, Proceedings of 2015 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). 〈10.1109/ISVLSI.2015.11〉. 〈lirmm-01234076〉
  • Marie-Lise Flottes, Sophie Dupuis, Papa-Sidy Ba, Bruno Rouzeyre. On the limitations of logic testing for detecting Hardware Trojans Horses. DTIS: Design and Technology of Integrated Systems in Nanoscale Era, Apr 2015, Naples, Italy. IEEE, Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 2015 10th International Conference on, 2015, 〈10.1109/DTIS.2015.7127362〉. 〈lirmm-01257837〉
  • Sophie Dupuis, Bruno Rouzeyre, Marie-Lise Flottes, Giorgio Di Natale, Papa-Sidy Ba. New Testing Procedure for Finding Insertion Sites of Stealthy Hardware Trojans. DATE: Design, Automation and Test in Europe, Mar 2015, Grenoble, France. IEEE, 2015. 〈lirmm-01141619〉
  • Raphael Andreoni Camponogara-Viera, Rodrigo Possamai Bastos, Jean-Max Dutertre, Olivier Potin, Marie-Lise Flottes, et al.. Validation Of Single BBICS Architecture In Detecting Multiple Faults. ATS: Asian Test Symposium, Nov 2015, Mumbai, India. 24th IEEE Asian Test Symposium, 2015, 〈https://www.ee.iitb.ac.in/ats15/〉. 〈lirmm-01234067〉
  • Stephan De Castro, Jean-Max Dutertre, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Figure of merits of 28nm Si technologies for implementing laser attack resistant security dedicated circuits. ISVLSI: IEEE Computer Society Annual Symposium on VLSI, Jul 2015, Montpellier, France. 2015, Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). 〈10.1109/ISVLSI.2015.76〉. 〈emse-01227138〉
  • Marie-Lise Flottes, João Azevedo, Giorgio Di Natale, Bruno Rouzeyre. Session-less based thermal-aware 3D-SIC test scheduling. ETS: European Test Symposium, May 2015, Cluj-Napoca, Romania. IEEE, 20th IEEE European Test Symposium, 2015, 〈10.1109/ETS.2015.7138732〉. 〈lirmm-01922990〉
  • Vincent Beroulle, Philippe Candelier, Stephan De Castro, Giorgio Di Natale, Jean-Max Dutertre, et al.. Laser-Induced Fault Effects in Security-Dedicated Circuits. Luc Claesen; Maria-Teresa Sanz-Pascual; Ricardo Reis; Arturo Sarmiento-Reyes. VLSI-SoC: Very Large Scale Integration and System-on-Chip, Oct 2014, Playa del Carmen, Mexico. 22nd IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration - System on a Chip, AICT-464, pp.220-240, 2015, IFIP Advances in Information and Communication Technology. 〈10.1007/978-3-319-25279-7_12〉. 〈hal-01383737〉
  • Feng Lu, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Layout-Aware Laser Fault Injection Simulation and Modeling: from physical level to gate level. DTIS: Design and Technology of Integrated Systems in Nanoscale Era, May 2014, Santorin, Greece. IEEE, 9th IEEE International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2014, 〈10.1109/DTIS.2014.6850665〉. 〈lirmm-01119592〉
  • Feng Lu, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Simulating Laser Effects on ICs, from Physical Level to Gate Level: a comprehensive approach. TRUDEVICE Workshop, May 2014, Paderborn, Germany. TRUDEVICE Workshop on Test and Fault Tolerance for Secure Devices, 2014, 〈http://www.ets14.de/media/PDFs/workshops/TRUDEVICE-ETS14-PreliminaryProgam〉. 〈lirmm-01119614〉
  • Feng Lu, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Customized Cell Detector for Laser-Induced-Fault Detection. IOLTS: International On-Line Testing Symposium, Jul 2014, Girona, Spain. IEEE 20th International On-Line Testing Symposium, pp.37-42, 2014, 〈10.1109/IOLTS.2014.6873669〉. 〈lirmm-01119576〉
  • Yassine Fkih, Pascal Vivet, Bruno Rouzeyre, Marie-Lise Flottes, Giorgio Di Natale, et al.. 2D to 3D Test Pattern Retargeting Using IEEE P1687 Based 3D DFT Architectures. ISVLSI: IEEE Computer Society Annual Symposium on VLSI, Jul 2014, Tampa, Florida, United States. pp.386-391, 2014, Proceedings of the 2014 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). 〈10.1109/ISVLSI.2014.83〉. 〈lirmm-01119605〉
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Hakim Zimouche. Built-In Self-Test for Manufacturing TSV Defects before bonding. IEEE. VTS: VLSI Test Symposium, Apr 2014, Napa, CA, United States. 32nd IEEE VLSI Test Symposium (VTS) pp.1-6, 2014, 〈10.1109/VTS.2014.6818771〉. 〈lirmm-00989682〉
  • Sophie Dupuis, Papa-Sidy Ba, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. A Novel Hardware Logic Encryption Technique for thwarting Illegal Overproduction and Hardware Trojans. IOLTS: International On-Line Testing Symposium, Jul 2014, Platja d'Aro, Girona, Spain. IEEE, 20th International On-Line Testing Symposium, pp.49-54, 2014, 〈http://tima.imag.fr/conferences/IOLTS/iolts14/〉. 〈10.1109/IOLTS.2014.6873671〉. 〈lirmm-01025275〉
  • Jean-Max Dutertre, Stephan De Castro, Alexandre Sarafianos, Noémie Boher, Bruno Rouzeyre, et al.. Laser attacks on integrated circuits: from CMOS to FD-SOI. DTIS: Design and Technology of Integrated Systems in Nanoscale Era, May 2014, Santorin, Greece. 9th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014, 〈10.1109/DTIS.2014.6850664〉. 〈emse-01099042〉
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Hakim Zimouche. TSVs Pre-Bond Testing: a test scheme for capturing BIST responses. 3D-Test: Testing Three-Dimensional Stacked Integrated Circuits, Sep 2013, Anaheim, CA, United States. IEEE, 4th IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits in conjunction with ITC / Test Week 2013 September 12-13, 2013 - Disneyland Hotel – Anaheim, California, USA, 2013, 〈http://www.pld.ttu.ee/3dtest/past_events/2013/〉. 〈lirmm-00989707〉
  • Yassine Fkih, Pascal Vivet, Bruno Rouzeyre, Marie-Lise Flottes, Giorgio Di Natale, et al.. 3D Design For Test Architectures Based on IEEE P1687. 3D-Test: Testing Three-Dimensional Stacked Integrated Circuits, Sep 2013, Anaheim, CA, United States. 4th IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits, 2013. 〈lirmm-00989717〉
  • Sophie Dupuis, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Identification of Hardware Trojans triggering signals. First Workshop on Trustworthy Manufacturing and Utilization of Secure Devices, May 2013, Avignon, France. 2013, 〈http://trudevice.com/Workshop/〉. 〈lirmm-00991360〉
  • Yassine Fkih, Pascal Vivet, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. A 3D IC BIST for pre-bond test of TSVs using Ring Oscillators. NEWCAS: New Circuits and Systems, Jun 2013, Paris, France. IEEE, 11th International International New Circuits and Systems Conference, pp.001-004, 2013, 〈http://www.newcas2013.org/〉. 〈lirmm-00838524〉
  • Feng Lu, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Laser-Induced Fault Simulation. EUROMICRO DSD/SEAA, Sep 2013, Santander, Spain. 16th Euromicro Conference on Digital System Design (DSD) & 39th Euromicro Conference on Software Engineering and Advanced Applications (SEAA), pp.609-614, 2013, 〈http://www.teisa.unican.es/dsd-seaa-2013/〉. 〈10.1109/DSD.2013.72〉. 〈lirmm-01430807〉
  • Jean Da Rolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. A smart test controller for scan chains in secure circuits. IOLTS: International On-Line Testing Symposium, Jul 2013, Chania, Greece. 19th IEEE International On-Line Testing Symposium, pp.228-229, 2013, 〈http://tima.imag.fr/conferences/iolts/iolts13/〉. 〈10.1109/IOLTS.2013.6604085〉. 〈lirmm-01430814〉
  • Hakim Zimouche, Marie-Lise Flottes, Bruno Rouzeyre, Giorgio Di Natale. A BIST Method for TSVs Pre-Bond Test. IDT'13: 8th IEEE International Design & Test Symposium, Dec 2013, Marrakesh, Morocco. pp.1-6, 2013, 〈http://idtsymposium.org/〉. 〈10.1109/IDT.2013.6727081〉. 〈lirmm-00989727〉
  • Rodrigo Possamai Bastos, Frank Sill Torres, Jean-Max Dutertre, Marie-Lise Flottes, Giorgio Di Natale, et al.. A single built-in sensor to check pull-up and pull-down CMOS networks against transient faults. PATMOS: Power and Timing Modeling, Optimization and Simulation, Sep 2013, Karlsruhe, Germany. 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation, pp.157-163, 2013, 〈http://www.patmos-conf.org/〉. 〈10.1109/PATMOS.2013.6662169〉. 〈lirmm-00968621〉
  • Jean-Max Dutertre, Rodrigo Possamai Bastos, Olivier Potin, Marie-Lise Flottes, Bruno Rouzeyre, et al.. Sensitivity tuning of a bulk built-in current sensor for optimal transient-fault detection. ESREF: European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, Sep 2013, Arcachon, France. IEEE Computer Society, 24th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, pp.B3c-2 #68, 2013. 〈hal-00872705〉
  • Rodrigo Possamai Bastos, Franck Sill Torres, Jean Max Dutertre, Marie-Lise Flottes, Giorgio Di Natale, et al.. A Bulk Built-in Sensor for Detection of Fault Attacks. HOST: Hardware-Oriented Security and Trust, Jun 2013, Austin, TX, United States. 6th Annual IEEE International Symposium on Hardware-Oriented Security and Trust, pp.51-54, 2013, 〈10.1109/HST.2013.6581565〉. 〈lirmm-01430800〉
  • Jean Da Rolt, Amitabh Das, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, et al.. A New Scan Attack on RSA in Presence of Industrial Countermeasures. Third International Workshop on Constructive Side-Channel Analysis and Secure Design, May 2012, Darmstadt, Germany. Springer, 7275, pp.89-104, 2012, Lecture Notes in Computer Science (LNCS). 〈http://cosade.cased.de/〉. 〈lirmm-00719986〉
  • Giorgio Di Natale, Sophie Dupuis, Bruno Rouzeyre. Is Side-Channel Analysis really reliable for detecting Hardware Trojans?. DCIS: Design of Circuits and Integrated Systems, Nov 2012, Avignon, France. 27th Conference on Design of Circuits and Integrated Systems, pp.238-242, 2012. 〈lirmm-00823477〉
  • Jean Da Rolt, Bruno Rouzeyre, Marie-Lise Flottes, Giorgio Di Natale, Amitabh Das, et al.. A Scan-based Attack on Elliptic Curve Cryptosystems in presence of Industrial Design-for-Testability Structures. IEEE International Symposium on Defect and Fault Tolerance in VLSI & Nanotechnology Systems, United States. http://www.dfts.org/, 2012. 〈lirmm-00744472〉
  • Jean Da Rolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. On-Chip Comparison for Testing Secure ICs. DCIS'2012: Conference on Design of Circuits and Integrated Systems, Nov 2012, Avignon, France. pp.112-117, 2012. 〈lirmm-00795205〉
  • Rodrigo Possamai Bastos, Frank Sill Torres, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Novel transient-fault detection circuit featuring enhanced bulk built-in current sensor with low-power sleep-mode. ESREF: European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, Oct 2012, Cagliari, Italy. 23rd European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, 2012. 〈hal-00867864〉
  • Jean Da Rolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Are Advanced DfT Structures Sufficient for Preventing Scan-Attacks?. VTS'12: 30th IEEE VLSI Test Symposium, Apr 2012, Maui, Hawai, United States. IEEE, pp.246-251, 2012, IEEE Catalog number : CFP12029-CDR. 〈http://www.tttc-vts.org/public_html/new/2012/index.php〉. 〈lirmm-00694536〉
  • Rodrigo Possamai Bastos, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Timing Issues for an Efficient Use of Concurrent Error Detection Codes. LATW: Latin American Test Workshop, Mar 2011, Porto de Galinhas, Brazil. 12th IEEE Latin American Test Workshop, pp.1-6, 2011, 〈http://www.feng.pucrs.br/~sisc/LATW/2011.html/〉. 〈10.1109/LATW.2011.5985933〉. 〈lirmm-00627427〉
  • Jean Da Rolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Scan Attacks and Countermeasures in Presence of Scan Response Compactors. ETS: European Test Symposium, May 2011, Trondheim, Norway. 16th IEEE European Test Symposium, pp.19-24, 2011, 〈http://www.ieee-ets.org/〉. 〈10.1109/ETS.2011.30〉. 〈lirmm-00647062〉
  • Jean Da Rolt, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre. New side-channel attack against scan chains. 9th CryptArchi Workshop (2011), Jun 2011, Bochum, Germany. pp.2, 2011, 〈http://labh-curien.univ-st-etienne.fr/cryptarchi/〉. 〈lirmm-00648575〉
  • Jean Da Rolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. New Security Threats Against Chips Containing Scan Chain Structures. HOST'11: IEEE International Symposium on Hardware-Oriented Security and Trust, San Diego, CA, United States. pp.105-110, 2011. 〈lirmm-00599690〉
  • Rodrigo Possamai Bastos, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. A New Bulk Built-in Current Sensor-Based Strategy for Dealing with Long-Duration Transient Faults in Deep-Submicron Technologies. IEEE. DFT'2011: International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Oct 2011, Vancouver, Canada. pp.302-308, 2011, 〈http://www.dfts.org/〉. 〈10.1109/DFT.2011.15〉. 〈lirmm-00701789〉
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Miroslav Valka, Denis Real. Power Consumption Traces Realignment to Improve Differential Power Analysis. DDECS'11: 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits ans Systems, Germany. pp.201-206, 2011. 〈lirmm-00592005〉
  • Rodrigo Possamai Bastos, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. How to Sample Results of Concurrent Error Detection Schemes in Transient Fault Scenarios?. RADECS: Radiation and Its Effects on Components and Systems, Sep 2011, Sevilla, Spain. IEEE, 12th European Conference on Radiation and Its Effects on Components and Systems, pp.635-642, 2012, 〈http://www.radecs.net/〉. 〈10.1109/RADECS.2011.6131361〉. 〈lirmm-00701776〉
  • Kaouthar Bousselam, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Evaluation of Concurrent Error Detection Techniques on the Advanced Encryption Standard. ETS: European Test Symposium, May 2010, Prague, Czech Republic. 15th IEEE European Test Symposium, 2010. 〈lirmm-00493247〉
  • Jérôme Di Battista, Philippe Perdu, Jc Courrège, Bruno Rouzeyre, Lionel Torres. Side-Channel Improvment by Laser Stimulation. Crypt'Archi'10: 8th Workshop on Cryptographic Architectures, Jun 2010, France. pp.N/A, 2010, 〈http://labh-curien.univ-st-etienne.fr/cryptarchi/workshop10/index.html〉. 〈lirmm-00575124〉
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Evaluation of Resistance to Differential Power Analysis: Execution Time Optimizations for Designers. DELTA'10: Fifth IEEE International Symposium on Electronic Design, Test and Application, Jan 2010, Ho Chi Minh City, Vietnam. pp.256-261, 2010. 〈lirmm-00539993〉
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Miroslav Valka. Waveforms re-Alignment to Improve DPA Attacks. CryptArchi'10: Cryptographic Architectures Embedded in Reconfigurable Devices, Jun 2010, Gif-sur-Yvette, France. 2010, 〈http://labh-curien.univ-st-etienne.fr/cryptarchi/workshop10/program.html〉. 〈lirmm-00539994〉
  • Jérôme Di Battista, Jc Courrège, Bruno Rouzeyre, Lionel Torres, Philippe Perdu. When Failure Analysis Meets Side-Channel Attacks. Lecture Notes in Computer Science. CHES'10: Cryptographic Hardware and Embedded System, Aug 2010, Santa Barbara, United States. Springer Verlag, 6225/2010, pp.188-202, 2010, 〈http://www.iacr.org/workshops/ches/ches2010/start.html〉. 〈10.1007/978-3-642-15031-9〉. 〈lirmm-00532636〉
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Ensuring High Testability without Degrading Security. DDECS'10: IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, Vienna, Austria. pp.6, 2010. 〈lirmm-00480710〉
  • Kaouthar Bousselam, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Evaluation of Concurrent Error Detection Techniques on the Advanced Encryption Standard. IOLTS'10: IEEE 16th International On-Line Testing Symposium, Jul 2010, Greece. pp.223 - 228, 2010, 〈http://tima.imag.fr/conferences/iolts/iolts10/index.htm〉. 〈10.1109/IOLTS.2010.5560196〉. 〈lirmm-00539232〉
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Execution Time Reduction of Differential Power Analysis Experiments. LATW'09: 10th Latin-American Test Workshop, Mar 2009, Armaçao dos Buzios, Brazil, pp.1-5, 2009, 〈10.1109/LATW.2009.4813819〉. 〈lirmm-00367712〉
  • Jérôme Di Battista, Philippe Perdu, Jc Courrège, Bruno Rouzeyre, Lionel Torres. Validation of Differential Light Emission Analysis on FPGA. SCS'09: International Conference on Signals, Circuits, Systems, Nov 2009, Djerba, Tunisia. 2009. 〈lirmm-00433563〉
  • Marie-Lise Flottes, Giorgio Di Natale, Paolo Maistri, Bruno Rouzeyre, Régis Leveugle. Ensuring High Testability without Degrading Security. ETS: European Test Symposium, May 2009, Seville, Spain. 14th IEEE European Test Symposium, 2009, 〈http://www.ieee-ets.org/〉. 〈lirmm-00407163〉
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Tutorial on Design For Testability & Digital Security. IEEE 10th Latin American Test Workshop, 2009, Buzios, Brazil. 2009, 〈http://inf.ufrgs.br/latw/〉. 〈lirmm-00407161〉
  • Erika Cota, Julien Dalmasso, Marie-Lise Flottes, Bruno Rouzeyre. Improving the Test of NoC-Based SoCs with Help of Compression Schemes. ISVLSI'08: IEEE Computer Society Annual Symposium on VLSI, Apr 2008, Montpellier, France, IEEE Computer Society Publishing Services, pp.139-144, 2008, 〈http://www.lirmm.fr/isvlsi2008/〉. 〈lirmm-00271574〉
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. An Integrated Validation Environment for Differential Power Analysis. IEEE Computer Society. DELTA'08: 4th IEEE International Symposium on Electronic Design, Test & Applications, Jan 2008, Hong Kong, pp.527-532, 2008, 〈http://www.ece.ust.hk/delta2008/〉. 〈lirmm-00220458〉
  • Solaiman Rahim, Jerome Rampon, Bruno Rouzeyre, Lionel Torres. Low Problem in Sequential Equivalence Checking. SAME'02: Sophia-Antipolis Forum on MicroElectronics, Sophia-Antipolis (France), France. pp. 52-57, 2002. 〈lirmm-00269332〉
  • Marie-Lise Flottes, Régis Poirier, Bruno Rouzeyre. A Simple and Effective Compression Scheme for Test Pins Reduction. HLDVT'02: IEEE International Workshop on High Level Design Validation and Test, Cannes (France), France. pp. 165-168, 2002. 〈lirmm-00269326〉
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. An Integrated Validation Environment for Differential Power Analysis. SAME'08: Sophia-Antipolis Forum on MicroElectronics 2008, Sep 2008, Sophia-Antipolis, France. 2008. 〈lirmm-00363796〉
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. A Reliable Architecture for Substitution Boxes in Integrated Cryptographic. DCIS'08: Conference on Design of Circuits and Integrated Systems, Nov 2008, CD-ROM, pp.27-32, 2008. 〈lirmm-00363783〉
  • Solaiman Rahim, Bruno Rouzeyre, Lionel Torres, Jerome Rampon. Matching in the Presence of don't Cares and Redundant Sequential Elements for Sequential Equivalence Checking. HLDVT'03: High Level Design Validation and Test Workshop, San Francisco (USA), France. pp. 129-135, 2003. 〈lirmm-00269707〉
  • Marie-Lise Flottes, Jean Pouget, Bruno Rouzeyre. Power-Constrained Test Scheduling for SoCs Under a "No Session" Scheme. SoC Design Methodologies, Montpellier, France, Kluwer Academic Publishers, pp.401-412, 2002. 〈lirmm-00268504〉
  • Z. Zeng, M. Ciesielski, Bruno Rouzeyre. Functional Test Generation Using Constraint Logic Programming. Kluwer Academic Publishers. SoC Design Methodologies - International Conference on Very Large Scale Integration of Systems-on-Chip, Montpellier, France, pp.375-386, 2002. 〈lirmm-00268536〉
  • Giorgio Di Natale, Marion Doulcier, Marie-Lise Flottes, Bruno Rouzeyre. A Reliable Architecture for the Advanced Encryption Standard. ETS: European Test Symposium, May 2008, Verbania, Italy. 13th IEEE European Test Symposium, pp.13-18, 2008. 〈lirmm-00285868〉
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. An Integrated Validation Environment for Differential Power Analysis. CryptArchi'08: Cryptographic Architectures Embedded in Reconfigurable Devices, Jun 2008, Tregastel, France. 2008. 〈lirmm-00332534〉
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Stuck-at-Faults Test using Differential Power Analysis. LPonTR'08: Workshop on Low Power Design Impact on Test and Reliability, May 2008, Italy. 2008, 〈http://www.cad.polito.it/~ets08/LPonTR/LPonTR.html〉. 〈lirmm-00332529〉
  • Marion Doulcier, Marie-Lise Flottes, Bruno Rouzeyre. L'auto-test d'un coeur de chiffrement AES. JNRDM'08 : Journées Nationales du Réseau Doctoral en Microélectronique, May 2008, France. pp.4, 2008, 〈http://www.u-bordeaux1.fr/jnrdm/〉. 〈lirmm-00325878〉
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Observability of Stuck-at-Faults with Differential Power Analysis. LATW'08: IEEE Latin American Test Workshop, Feb 2008, Mexico. pp.N/A, 2008, 〈http://www-elec.inaoep.mx/latw2008/index.php〉. 〈lirmm-00295498〉
  • Giorgio Di Natale, Marion Doulcier, Marie-Lise Flottes, Bruno Rouzeyre. Low Cost Self-Test of Crypto-Devices. WDSN'08: 2nd Workshop on Dependable and Secure Nanocomputing, Jun 2008, Anchorage, Canada, United States. pp.41-46, 2008, 〈http://www.ece.cmu.edu/~koopman/dsn08/index.html〉. 〈lirmm-00295108〉
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. An Integrated Validation Environment for Differential Power Analysis. DELTA: Electronic Design, Test and Applications, Jan 2008, Hong Kong, China. 4th IEEE International Symposium on Electronic Design, Test and Applications, pp.527-532, 2008, 〈10.1109/DELTA.2008.61〉. 〈lirmm-00407165〉
  • Marion Doulcier, Marie-Lise Flottes, Bruno Rouzeyre. AES-based BIST: Self-test, Test Pattern Generation and Signature Analysis. DELTA'08: 4th IEEE International Symposium on Electronic Design, Test & Applications, Jan 2008, Hong-Kong, IEEE, pp.314-321, 2008, 〈http://www.ece.ust.hk/delta2008/〉. 〈lirmm-00258769〉
  • Marie-Lise Flottes, Marion Doulcier, Bruno Rouzeyre. Utilisation de ressources cryptographiques pour le test des circuits sécurisés. colloque du GDR SOC-SIP 2007, Jun 2007, Jussieu - Paris, France. 2007. 〈lirmm-00203332〉
  • Julien Dalmasso, Marie-Lise Flottes, Bruno Rouzeyre. Test Data Compression and TAM Design. IFIP VLSI-SOC 2007 - IFIP WG 10.5 International Conference on Very Large Scale Integration, Oct 2007, Atlanta, GA, USA, pp.178-183, 2007. 〈lirmm-00186171〉
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. A Novel Parity Bit Scheme for SBOX in AES Circuits. DDECS'07: Design and Diagnostics of Electronic Cicruits and Systems, Apr 2007, Cracovie, Pologne, IEEE, pp.267-271, 2007. 〈lirmm-00141799〉
  • Marion Doulcier, Marie-Lise Flottes, Bruno Rouzeyre. AES vs LFSR Based Test Pattern Generation: A Comparative Study. LATW: Latin American Test Workshop, Mar 2007, Cuzco, Peru. IEEE, 8th IEEE Latin American Test Workshop, pp.314-321, 2007. 〈lirmm-00138831〉
  • Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre, Marion Doulcier. Test and Security. CryptArchi'07: Cryptographic Architectures Embedded in Reconfigurable Devices, Jun 2007, Montpellier, France. 2007, 〈http://cryptarchi.univ-st-etienne.fr/workshop07/index.htm〉. 〈lirmm-00163017〉
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. On-Line Self-Test of AES Hardware Implementations. DSN'07: Workshop on Dependable and Secure Nanocomputing, Jun 2007, Edinburgh, United Kingdom. 2007. 〈lirmm-00163405〉
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. An On-Line Fault Detection Scheme for SBoxes in Secure Circuits. IEEE. IOLTS'07: 13th IEEE International On-Line Testing Symposium, Jul 2007, Heraklion, Crete, Greece, pp.57-62, 2007. 〈lirmm-00163244〉
  • Julien Dalmasso, Marie-Lise Flottes, Bruno Rouzeyre. Fitting ATE Channels with Scan Chains: A Comparison Between a Test Data Compression Technique and Serial Loading of Scan Chains. DELTA'06: Third IEEE International Workshop on Electronics DesignTest & Applications, Kuala Lumpur (Malaysia), IEEE, pp.295-300, 2006. 〈lirmm-00102704〉
  • David Hély, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre. A Secure Scan Design Methodology. LATW'06: 7th IEEE Latin American Test Workshop, Mar 2006, Buenos Aires, Argentina. pp.81-86, 2006. 〈lirmm-00102752〉
  • David Hely, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre. Scan Pattern Watermarking. LATW'06: 7th IEEE Latin American Test Workshop, Mar 2006, Buenos Aires, pp.63-67, 2006. 〈lirmm-00102753〉
  • Julien Dalmasso, Marie-Lise Flottes, Bruno Rouzeyre. Compression de Données de Test : Réduction du Nombre de Broches et Gain en Temps de Test. JNRDM: Journées Nationales du Réseau Doctoral de Microélectronique, May 2006, Rennes, France. 9ièmes Journées Nationales du Réseau Doctoral de Microélectronique, 2006. 〈lirmm-00102830〉
  • David Hély, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre. Secure Scan Techniques: a Comparison. IOLTS'06: 12th International On-Line Testing Symposium, Jul 2006, Como, Italy, IEEE, pp.119-124, 2006, 〈10.1109/IOLTS.2006.55〉. 〈lirmm-00102857〉
  • David Hély, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre. A secure Scan Design Methodology. DATE: Design, Automation and Test in Europe, Mar 2006, Munich, Germany. IEEE, Proceedings of the Design Automation & Test in Europe Conference, pp.1177-1178, 2006, 〈10.1109/DATE.2006.244019〉. 〈lirmm-00132516〉
  • Mathieu Scholivé, Vincent Beroulle, Chantal Robach, Marie-Lise Flottes, Bruno Rouzeyre. Mutation Sampling Technique for the Generation of Structural Test Data. DATE: Design, Automation and Test in Europe, 2005, Munich, Germany. IEEE, pp.1022, 2005. 〈lirmm-00105978〉
  • David Hely, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre. Scan Design and Secure Chips : Can They Work Together. SAME'05: Sophia-Antipolis Forum on MicroElectronics, Oct 2005, Sophia-Antipolis, France. 2005. 〈lirmm-00106546〉
  • David Hely, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre. Test Control for Secure Scan Designs. ETS: European Test Symposium, May 2005, Tallinn, Estonia. 10th IEEE European Test Symposium, pp.190-195, 2005. 〈lirmm-00106011〉
  • Mathieu Scholivé, Vincent Beroulle, Chantal Robach, Marie-Lise Flottes, Bruno Rouzeyre. Mutation sampling technique for the generation of structural test data. 6th IEEE Latin American Test Workshop, Mar 2005, Salvador, Bahia, Brazil. 2005. 〈hal-00378490〉
  • Mathieu Scholivé, Vincent Beroulle, Chantal Robach, Marie-Lise Flottes, Bruno Rouzeyre. Mutation Sampling Technique for the Generation of Structural Test Data. EDAA - European design and Automation Association. DATE: Design, Automation and Test in Europe, Mar 2005, Munich, Germany. 2, pp.1022-1023, 2005. 〈hal-00181680〉
  • Solaiman Rahim, Jerome Rampon, Bruno Rouzeyre, Lionel Torres. An Efficient Flip-Flops Matching Engine. DDECS'04: 7th IEEE International Workshop on Design and Diagnostics of Electronic Circuits and Systems, Apr 2004, Slovakia, pp.105-113, 2004. 〈lirmm-00108773〉
  • Marie-Lise Flottes, Régis Poirier, Bruno Rouzeyre. An Arithmetic Structure for Test Data Horizontal Compression. DATE: Design, Automation and Test in Europe, Feb 2004, Paris, France. pp.428-434, 2004. 〈lirmm-00108837〉
  • Marie-Lise Flottes, Régis Poirier, Bruno Rouzeyre. On Using Test Vector Differences for Reducing Test Pin Numbers. DELTA'04: 2nd International Workshop on Electronic DesignTest and Applications, Jan 2004, Perth (Australia), IEEE Computer Society, pp.275-280, 2004. 〈lirmm-00108832〉
  • L. Krundel, S. Kumar Goel, E.J. Marinissen, Marie-Lise Flottes, Bruno Rouzeyre. User-Constrained Test Architecture Design for Modular SOC Testing. ETS: European Test Symposium, May 2004, Ajaccio, Corsica, France. 9th IEEE European Test Symposium, pp.80-85, 2004, 〈10.1109/ETSYM.2004.1347611〉. 〈lirmm-00108903〉
  • David Hely, Marie-Lise Flottes, Frédéric Bancel, Bruno Rouzeyre, Nicolas Berard, et al.. Scan Design and Secure Chip. IOLTS'04: 10th International On-Line Testing Symposium, Jul 2004, Madeira Island, Portugal. IEEE, pp.219-224, 2004. 〈lirmm-00108909〉
  • Mathieu Scholivé, Vincent Beroulle, Chantal Robach, Marie-Lise Flottes, Bruno Rouzeyre. Software-Based Testing of Sequential VHDL Descriptions. ETW: European Test Workshop, Mar 2003, Maastricht, Netherlands. pp.199-200, 2003. 〈lirmm-00269437〉
  • Solaiman Rahim, Bruno Rouzeyre, Lionel Torres, Jerome Rampon. Matching in the Presence of don't Cares and Redundant Sequential Elements for Sequential Equivalence Checking. HLDVT'03: High Level Design Validation and Test Workshop, San Francisco, United States. pp.129-135, 2003. 〈lirmm-00269474〉
  • Solaiman Rahim, Bruno Rouzeyre, Lionel Torres, Jerome Rampon. Matching in the Presence of don't Cares and Redundant Sequential Elements for Sequential Equivalence Checking. HLDVT'03: High Level Design Validation and Test Workshop, San Francisco (USA), France. pp. 129-135, 2003. 〈lirmm-00191957〉
  • Julien Pouget, Erik Larsson, Zebo Peng, Marie-Lise Flottes, Bruno Rouzeyre. An Efficient Approach to SoC Wrapper Design, TAM Configuration and Test Scheduling. ETW: European Test Workshop, 2003, Maastricht, Netherlands. IEEE, pp.51-56, 2003. 〈lirmm-00191948〉
  • Maciej Ciesielski, Priyank Kalla, Zhihong Zheng, Bruno Rouzeyre. Taylor Expansion Diagrams: A Compact, Canonical Representation with Applications to Symbolic Verification. DATE: Design, Automation and Test in Europe, Mar 2002, Paris, France. Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings, pp.285-289, 2002, 〈10.1109/DATE.2002.998286〉. 〈lirmm-00268497〉
  • Marie-Lise Flottes, Julien Pouget, Bruno Rouzeyre. A Heuristic for Test scheduling at System Level. DATE: Design, Automation and Test in Europe, Mar 2002, Paris, France. pp.1124-1124, 2002, 〈10.1109/DATE.2002.998480〉. 〈lirmm-00268503〉

Poster12 documents

  • Mathieu Da Silva, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Scan chain encryption in Test Standards. SURREALIST: SecURity, REliAbiLity, test, prIvacy, Safety and Trust of Future Devices, May 2018, Bremen, Germany. Workshop on SecURity, REliAbiLity, test, prIvacy, Safety and Trust of Future Devices, 2018, 〈http://www.lirmm.fr/surrealist18/〉. 〈lirmm-01882578v2〉
  • Mathieu Da Silva, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Scan chain encryption, a countermeasure against scan attacks. PHISIC: Practical Hardware Innovations in Security Implementation and Characterization, May 2018, Gardanne, France. Workshop on Practical Hardware Innovations in Security Implementation and Characterization, 2018, 〈http://phisic2018.emse.fr〉. 〈lirmm-01882565v2〉
  • Mathieu Da Silva, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre. Sécurité des moyens de test des SoC. Journée thématique des GDR SoC² et Sécurité Informatique : Sécurité des SoC complexes hétérogènes – de la TEE au matériel, Sep 2018, Paris, France. 2018. 〈lirmm-01882552〉
  • Mathieu Da Silva, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Scan Chain Encryption for the Test, Diagnosis and Debug of Secure Circuits. SETS: South European Test Seminar, Mar 2017, Alpe d'Huez, France. 2017, 〈http://tima.univ-grenoble-alpes.fr/conferences/sets/2017/〉. 〈lirmm-01892667〉
  • Papa-Sidy Ba, Sophie Dupuis, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre. Detection and Prevention of Hardware Trojan through Logic Testing. TRUDEVICE, Nov 2016, Barcelona, Spain. 4th Workshop on Trustworthy Manufacturing and Utilization of Secure Devices, Manufacturing test of secure devices / Reverse engineering countermeasures / Other topics, pp.#33, 2016, Posters IV. 〈https://trudevice2016.eel.upc.edu/〉. 〈lirmm-01430007〉
  • Jean-Max Dutertre, Rodrigo Possamai Bastos, Olivier Potin, Marie-Lise Flottes, Giorgio Di Natale, et al.. Design of Bulk Built-In Current Sensors to Detect Single Event Effects and Laser-Induced Fault Injection Attempts. Joint MEDIAN–TRUDEVICE Open Forum, Sep 2014, Amsterdam, Netherlands. 2014. 〈emse-01099040〉
  • Giorgio Di Natale, Marie-Lise Flottes, Feng Lu, Bruno Rouzeyre. tLIFTING : A Multi-level Delay-annotated Fault Simulator for Digital Circuits. DCIS'2012: XVII Conference on Design of Circuits and Integrated Systems, Nov 2012, avignon, France. pp.1, 2012, 〈http://www.lirmm.fr/dcis2012/〉. 〈lirmm-00799892〉
  • Rodrigo Possamai Bastos, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Calibrating Bulk Built-in Current Sensors for Detecting Transient Faults. Colloque GDR SoC-SiP, 2012, Lyon, France. 2012, Colloque National du Groupement de Recherche System-On-Chip et System-In-Package. 〈lirmm-00715126〉
  • Rodrigo Possamai Bastos, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Timing Issues of Transient Faults in Concurrent Error Detection Schemes. GdR SoC-SiP'2011: Colloque national du Groupement de Recherche System-On-Chip et System-In-Package, Lyon, France. http://www2.lirmm.fr/~w3mic/SOCSIP/, 2011, 〈http://www2.lirmm.fr/~w3mic/SOCSIP/〉. 〈lirmm-00701798〉
  • Erika Cota, Julien Dalmasso, Marie-Lise Flottes, Bruno Rouzeyre. Improving NoC-based Testing Through Compression Schemes. DATE: Design, Automation and Test in Europe, Apr 2007, Nice, France. 2007, 〈http://www.date-conference.com/conference/2007/prog/〉. 〈lirmm-00170833〉
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. A Dependable Parallel Architecture for SBoxes. ReCoSoc'07: International Workshop on Reconfigurable Communication Centric System-On-Chips, Jun 2007, Montpellier, France. pp.CD-ROM, 2007. 〈lirmm-00163414〉
  • Julien Dalmasso, Marie-Lise Flottes, Bruno Rouzeyre. TAM Design and Test Data Compression for SoC Test Cost Reduction. ETS: European Test Symposium, May 2007, Freiburg, Germany. 12th IEEE European Test Symposium, pp.241-246, 2007. 〈lirmm-00159044〉

Ouvrage (y compris édition critique et traduction)1 document

  • Florence Azaïs, Serge Bernard, Yves Bertrand, Marie-Lise Flottes, Patrick Girard, et al.. Test de Circuits et de Systèmes Intégrés. Collection EGEM, Ed.Hermès, 2004, 2-7462-0864-4. 〈lirmm-00109158〉

Chapitre d'ouvrage4 documents

Autre publication19 documents

  • Patrick Girard, Serge Bernard, Florence Azaïs, Alberto Bosio, Luigi Dilillo, et al.. Rapport Technique intermédiaire, Contrat TOETS CT 302, Programme CEE CATRENE. 2011. 〈lirmm-00679018〉
  • Patrick Girard, Serge Bernard, Florence Azaïs, Alberto Bosio, Luigi Dilillo, et al.. Rapport Technique de fin d'année, Contrat TOETS CT 302, Programme CEE CATRENE. 2011. 〈lirmm-00679022〉
  • Patrick Girard, Florence Azaïs, Serge Bernard, Alberto Bosio, Luigi Dilillo, et al.. TOETS CT302 - Programme CEE CATRENE - Summary Technical Report 2S-2009 - Rapport Technique de Fin d'année. 2010. 〈lirmm-00461745〉
  • Patrick Girard, Serge Bernard, Florence Azaïs, Alberto Bosio, Luigi Dilillo, et al.. Contrat TOETS CT 302 - Programme CEE CATRENE (Rapport Intermédiaire). 2010. 〈lirmm-00504873〉
  • Patrick Girard, Serge Bernard, Alberto Bosio, Luigi Dilillo, Marie-Lise Flottes, et al.. Rapport Technique de fin de Contrat NanoTEST 2A702, Programme CEE MEDEA+. 2009. 〈lirmm-00406974〉
  • Marion Doulcier, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Test and Harware Security. 2008. 〈lirmm-00365276〉
  • Patrick Girard, Serge Bernard, Alberto Bosio, Marie-Lise Flottes, Serge Pravossoudovitch, et al.. Contrat NanoTEST 2A702 - Programme CEE MEDEA - Rapport Technique intermédiaire. 2007. 〈lirmm-00199966〉
  • Patrick Girard, Serge Bernard, Alberto Bosio, Marie-Lise Flottes, Serge Pravossoudovitch, et al.. Contrat NanoTEST 2A702 - Programme CEE MEDEA - Rapport Technique de fin d'année. 2007. 〈lirmm-00199958〉
  • Patrick Girard, Serge Bernard, Marie-Lise Flottes, Christian Landrault, Serge Pravossoudovitch, et al.. Contrat NanoTEST 2A702, Programme CEE MEDEA +. 2006. 〈lirmm-00130759〉
  • Patrick Girard, Serge Bernard, Marie-Lise Flottes, Christian Landrault, Serge Pravossoudovitch, et al.. Contrat NanoTEST 2A702 - Programme CEE MEDEA+. 12927. 2006. 〈lirmm-00102699〉
  • Patrick Girard, Serge Bernard, Marie-Lise Flottes, Christian Landrault, Serge Pravossoudovitch, et al.. Contrat NanoTEST 2A702, Programme CEE MEDEA+. 2006. 〈lirmm-00130758〉
  • Bruno Rouzeyre, Marie-Lise Flottes. Test Circuits Sécurisés 2. 11737. 2004, 2 p. 〈lirmm-00109182〉
  • Patrick Girard, Michel Renovell, Serge Bernard, Marie-Lise Flottes, Serge Pravossoudovitch, et al.. Advanced Solutions for Innovative SOC Testing in Europe. 12702. 2004. 〈lirmm-00109190〉
  • Patrick Girard, Michel Renovell, Florence Azaïs, Serge Bernard, Marie-Lise Flottes, et al.. Advanced Solutions for Innovative SOC Testing in Europe, Contrat CEE ASSOCIATE A503, Programme MEDEA+ (Rapport Technique de Fin d'Année). 10072. 2003, pp.P nd. 〈lirmm-00269749〉
  • Bruno Rouzeyre, Marie-Lise Flottes. Test Circuits Sécurisés 1. 11738. 2003, 3 p. 〈lirmm-00269804〉
  • Patrick Girard, Michel Renovell, Florence Azaïs, Yves Bertrand, Marie-Lise Flottes, et al.. Advanced Solutions for Innovative SOC Testing in Europe, Contrat CEE ASSOCIATE A503, Programme MEDEA+ (Rapport Technique Intermédiaire). 10042. 2003, pp.P nd. 〈lirmm-00269720〉
  • Bruno Rouzeyre, Marie-Lise Flottes. Test Circuits Sécurisés 1. 11738. 2003, 3 p. 〈lirmm-00269490〉
  • Bruno Rouzeyre, Marie-Lise Flottes. Test Circuits Sécurisés 1. 11738. 2003, pp.3. 〈lirmm-00191973〉
  • Patrick Girard, Florence Azaïs, Serge Bernard, Yves Bertrand, Marie-Lise Flottes, et al.. Advanced Solutions for Innovative SOC Testing in Europe. 7724. 2002. 〈lirmm-00268586〉

Rapport3 documents

  • Nadia El Mrabet, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Jean-Claude Bajard. Differential Power Analysis against the Miller Algorithm. RR-08021, 2008. 〈lirmm-00323684〉
  • Patrick Girard, Serge Bernard, Alberto Bosio, Marie-Lise Flottes, Serge Pravossoudovitch, et al.. Contrat Nano TEST 2A702, Programme CEE MEDEA (Rapport Technique de fin d'année). 08026, 2008. 〈lirmm-00344408〉
  • Patrick Girard, Serge Bernard, Alberto Bosio, Marie-Lise Flottes, Serge Pravossoudovitch, et al.. Contrat Nano TEST 2A702, Programme CEE MEDEA (Rapport Intermédiaire). 08027, 2008. 〈lirmm-00344415〉