Bruno Robisson

**Contact** Adress : Bât 351, CEA Cadarache, 13108 Saint-Paul Lez Durance, France E-mail : bruno.robisson@cea.fr Phone : +33(0)442253741 Data bases :[linkedin](https://www.linkedin.com/in/bruno-robisson-0933651/), [Google scholar](http://scholar.google.com/citations?user=uFxn0vsAAAAJ&hl=fr) **Experience** • 2020/07 – ... : Researcher at Commissariat à l'Energie Atomiques et aux Energies Alternatives (CEA), CEA-Liten/DTS, Researcher in the Photovoltaics Laboratory • 2016/10 – 2020/06 : Researcher at Commissariat à l'Energie Atomiques et aux Energies Alternatives (CEA), CEA-Tech Region institute, Researcher in the Photovoltaics Laboratory • 2013/04 – 2016/09 : Researcher at Commissariat à l'Energie Atomiques et aux Energies Alternatives (CEA), CEA-Tech Region institute, head of the team “ Secure Architectures and Systems ”( [SAS](http://cmp.mines-stetienne.fr/content/689-department-secure-architectures-and-systems-sas) ) • 2010 – 2013/04 : Researcher at CEA-Leti institute, deputy director of SAS • 2001 – 2010 : Researcher at CEA-Leti institute **Education** • 2012: Habilitation à Diriger des Recherches - “ Protection of integrated circuits against physical attacks ” - Paris VI - 12 december 2012 at Paris • 2001: PhD in computer science - “ Scientific discovery of power electronics circuits ” - Paris VI - 21 september 2001 at Paris • 1998: Master of science – “ Artificial Intelligence, Pattern Recognition and Applications ” - Paris VI • 1997: “ Agrégation ” (French teaching grade) of electrical engineering - ENS Cachan **Skills and expertise** • Electric Vehicle (EV) Grid Integration, Smart Charging, e-mobility market • Electricity market, electricity balancing market, grid codes • Solar photovoltaics • Design of systems secure against physical attacks • Modeling and simulation of physical systems • Computer science, artificial intelligence • Electronics, electrotechnics, automation **PhD students** • Van-Lap Ngo, "Controling EV charging as a flexilibity load for the network" with S. Guillemin (CEA) and G. Guyot (CEA). Forecasted in october 2027. • Charly Boudot, "Innovative nuclear systems: new strategies for the grid reliability" with Y. Besanger (Grenoble-INP), J.-B. Droin (CEA) and P. Sciora (CEA). Defended the 18 october 2023 at Cadarache. • Florian Selot, "Formalisation and simulation of the french electric grid balancing mecanism" with C. Vagliot-Gaudard (CEA). Defended the 11 May 2023 at Cadarache. • Thierno Barry, "Securing Software Against Fault Attacks at Compile Time" with D. Couroussé (CEA). Defended the 24 november 2017 in Grenoble. • Clément Champeix, “ Securing integrated circuits against laser fault injection ” with J.-M. Dutertre (ENSMSE) and M. Lisart (STMicroelectronics). Defended the 15 december 2016 at Gardanne. • Ingrid Exurville, “ Non intrusive detection of hardware Trojan ” with J.-B. Rigaud (ENSMSE). Defended the 30 october 2015 at Gardanne. • Nicolas Moro, “ Securing assembly code against fault attacks “ with E. Encrenaz-Tiphene (LIP6) and Karine Heydemann (LIP6). Defended the 13 november 2014 at Paris. • Loïc Zussa, “ Analysis of faults created by timing violation and enabling the physical cryptanalysis of secure circuits ” with A. Tria (CEA) and J.-M. Dutertre (ENSMSE). Defended the 10 october 2014 at Gardanne. • François Poucheret, “ Methods and tools for electromagnetic fault injections ” with Ph. Maurine (LIRMM) defended the 23 november 2012 at Montpellier. • Minh Huu Nguyen, “ Protection of processors against fault and side channel attacks ” with N. Drach-Temam (LIP6) defended the 21 september 2011 at Paris. • Selma Laabidi, “ Design methods to protect integrated circuits against correlation attacks ” with Ph. Collot (ENSMSE) defended the19 janvier 2010 at Gardanne. **Teaching** • 2010- 2021 : Mines de Saint-Etienne Engineer school, 3th year cycle ISMIN (Design of Computer Systems option), course “ Simulation d’entretien de recrutement “ (6h) • 2009- 2016 : Mines de Saint-Etienne Engineer school, 3th year cycle ISMIN (Mobility and Security option), course “ Side channel and fault attacks“ (15h) • 2005-today: Mines de Saint-Etienne Engineer school, 1st year cycle ICM (Micro-electronics option), course “ VLSI design“ (7h) • 2009: Mines de Saint-Etienne Engineer school, continuing education, course “Side channel and fault attacks” (20h) • 2007: Mines de Saint-Etienne Engineer school, Master SISA, course “ Side channel and fault attacks” (28h) • 2005: Mines de Saint-Etienne Engineer school, 2nd year cycle ISMEA, laboratory “ FPGA programming“ (15h) • 1998-2001: Pierre et Marie Curie university, 1st et 2nd year MIAS, laboratory and course “ Assembly Langage , Algorithmic et Visual Basic “ (92h/year)