Marc Bocquet

Enseignant Chercheur (Professeur des universités) à l'université d'Aix-Marseille.

Documents

Présentation

Professeur des Universités - 63ème section CNU ============================================== Unités de rattachement actuelles -------------------------------- ### Laboratoire de recherche : Institut Matériaux Microélectronique Nanosciences de Provence (Im2np) Im2np, UMR CNRS 7334 et Université d'Aix-Marseille <http://www.im2np.fr> Equipe Mémoires - Département ASCE ### Composante d'enseignement : IUT dpt GEII de Marseille <https://iut.univ-amu.fr/departements/geii-marseille> Responsabilités Administratives ### Laboratoire - Depuis 2017 : Co-responsable de l'équipe Mémoires de l'IM2NP - Depuis 2017 : Membre du conseil scientifique de l'IM2NP ### Unité de Formation - 2019-2020 : Co-responsable de la 2ème année du cycle préparatoire intégrée de Polytech Marseille - 2014-2019 : Responsable d'année du département MT de Polytech Marseille - 2012-2014 : Responsable d'un parcours d'enseignement au département MT de Polytech Marseille Diplômes -------- - Juin 2017 : Habilitation à diriger les recherches (HDR), Université d’Aix-Marseille. - Novembre 2009 : Thèse de doctorat en Micro&NanoElectronique de l'INPG, Grenoble. - 2005-2006 : Master NanoTechnologies Université Joseph Fourier, Grenoble, mention bien - 2003-2006 : Diplôme d'ingénieur ENSERG - INPG, Grenoble, mention très bien Activité d'enseignement ----------------------- Volume : Environ 2500 HETD enseignées depuis 2006 Niveaux : Cycle préparatoire (2A), école d'ingénieur (3A-4A-5A), formation continue Matières enseignés : Base de l'électronique numérique, microcontrôleur, électrotechnique, physique et technologie des composants à semi-conducteur, mémoires non-volatiles Thématiques de recherche ------------------------ ### Mots-clefs thématiques : Technologies mémoires émergentes, micro-nanoélectronique, électronique flexible, mémoires non-volatiles, mémoires résistives, RRAM, CBRAM, PCM, FRAM ### Compétences : Microscopie champ proche (AFM, EFM, KPFM, C-AFM), caractérisation électrique sous pointes, modélisation physique, modélisation compacte ### Thèmes : - Modélisation et caractérisation des mémoires innovantes : RRAM, PCRAM, FRAM - Développement technologique de dispositifs mémoires sur support souple\\\\ - Optimisation de nouvelles architectures mémoires de type EEPROM/Flash Projets de recherche -------------------- Implication en tant que participant (P) ou coordinateur (C) : - ANR Neuronic (2019-2023) (C) - IPCEI Nano2022 (2019-2022) (C) - UNICO Chist-ERA (2019-2022) (P) - ANR Reflex (2012-2015) (P) - ANR Dipmem (2012-2015) (P) - Carnot POLYMEM (2014) (P) Expertises Nationales --------------------- - Participation à des jurys de thèse : 2 en tant que président, 4 en tant que rapporteur et 1 en tant que Examinateur - Depuis 2016 : Expertise de dossiers AGIR-PEPS, ANR, IRS, projet region. - 2013 : Membre de la commission de Spécialité de la 63ème section collège B Encadrement doctoral -------------------- - 4 thèses en co-encadrement soutenues - 2 thèses en co-encadrement en cours. - Co-encadrement de thèses sous contrat CIFRE et CTBU CEA. Dissémination scientifique -------------------------- - 105 publications - 25 revues internationales à comité de lecture. - 54 proceedings de conférences internationales à comité de lecture. - 2 articles de vulgarisation scientifiques. - 7 conférences invitées - 1 brevet.

Publications

jean-michel-portal

	Voltage-dependent synaptic plasticity: Unsupervised probabilistic Hebbian plasticity rule based on neurons membrane potential Nikhil Garg , Ismael Balafrej , Terrence Stewart , Jean-Michel Portal , Marc Bocquet Frontiers in Neuroscience, 2022, 16, 983950, 12 p. ⟨10.3389/fnins.2022.983950⟩ Article dans une revue hal-03834905v1
	Model of the Weak Reset Process in HfO x Resistive Memory for Deep Learning Frameworks Atreya Majumdar , Marc Bocquet , Tifenn Hirtzlin , Axel Laborieux , Jacques-Olivier Klein IEEE Transactions on Electron Devices, 2021, 68 (10), pp.4925-4932. ⟨10.1109/TED.2021.3108479⟩ Article dans une revue hal-03372056v1
	OxRAM+OTS optimization for Binarized Neural Network hardware implementation Joel Minguet Lopez , Tifenn Hirtzlin , Manon Dampfhoffer , Laurent Grenouillet , Lucas Reganaz Semiconductor Science and Technology, 2021, 37 (1), pp.014001. ⟨10.1088/1361-6641/ac31e2⟩ Article dans une revue hal-03418653v1
	Write Termination circuits for RRAM : A Holistic Approach From Technology to Application Considerations Alexandre Levisse , Marc Bocquet , Marco Rios , Mouhamad Alayan , Mathieu Moreau IEEE Access, 2020, pp.109297-109308. ⟨10.1109/ACCESS.2020.3000867⟩ Article dans une revue hal-02863232v1
	Implementation of Ternary Weights With Resistive RAM Using a Single Sense Operation per Synapse Axel Laborieux , Marc Bocquet , Hirtzlin Tifenn , Jacques-Olivier Klein , Etienne Nowak IEEE Transactions on Circuits and Systems I: Regular Papers, 2020, pp.1-10. ⟨10.1109/TCSI.2020.3031627⟩ Article dans une revue hal-02983778v1
	Digital Biologically Plausible Implementation of Binarized Neural Networks With Differential Hafnium Oxide Resistive Memory Arrays Tifenn Hirtzlin , Marc Bocquet , Bogdan Penkovsky , Jacques-Olivier Klein , Etienne Nowak Frontiers in Neuroscience, 2020, 13, ⟨10.3389/fnins.2019.01383⟩ Article dans une revue hal-02436382v1
	Switching Event Detection and Self-Termination Programming Circuit for Energy Efficient ReRAM Memory Arrays M. Alayan , E. Muhr , A. Levisse , Marc Bocquet , M. Moreau IEEE Transactions on Circuits and Systems II: Express Briefs, 2019, 66 (5), pp.748-752. ⟨10.1109/TCSII.2019.2908967⟩ Article dans une revue hal-02158840v1
	Stochastic Computing for Hardware Implementation of Binarized Neural Networks Tifenn Hirtzlin , Bogdan Penkovsky , Marc Bocquet , Jacques-Olivier Klein , Jean-Michel Portal IEEE Access, 2019, pp.1-1. ⟨10.1109/ACCESS.2019.2921104⟩ Article dans une revue hal-02158846v1
	Phase-Change Memory: A Continuous Multilevel Compact Model of Subthreshold Conduction and Threshold Switching Corentin Pigot , Fabien Gilibert , Marina Reyboz , Marc Bocquet , Paola Zuliani Japanese Journal of Applied Physics, inPress, 57 (4S), ⟨10.7567/JJAP.57.04FE13⟩ Article dans une revue hal-01737915v1
	Comprehensive Phase-Change Memory Compact Model for Circuit Simulation Corentin Pigot , Marc Bocquet , Fabien Gilibert , Marina Reyboz , Olga Cueto IEEE Transactions on Electron Devices, 2018, pp.1 - 8. ⟨10.1109/TED.2018.2862155⟩ Article dans une revue hal-01869957v1
	Design and Simulation of a 128 kb Embedded Nonvolatile Memory Based on a Hybrid RRAM (HfO$_2$ )/28 nm FDSOI CMOS Technology Jean-Michel Portal , Marc Bocquet , Santhosh Onkaraiah , Mathieu Moreau , Hassen Aziza IEEE Transactions on Nanotechnology, 2017, 16, pp.677 - 686. ⟨10.1109/TNANO.2017.2703985⟩ Article dans une revue hal-01745418v1
	A Built-In Self-Test Structure (BIST) for Resistive RAMs Characterization: Application to Bipolar OxRRAM Hassen Aziza , Marc Bocquet , Mathieu Moreau , Jean-Michel Portal Solid-State Electronics, 2015, 103, pp.73 - 78. ⟨10.1016/j.sse.2014.09.005⟩ Article dans une revue hal-01737300v1
	Synchronous Non-Volatile Logic Gate Design Based on Resistive Switching Memories Weisheng Zhao , Mathieu Moreau , Erya Deng , Yue Zhang , Jean-Michel Portal IEEE Transactions on Circuits and Systems I: Regular Papers, 2014, 61 (2), pp.443 - 454. ⟨10.1109/TCSI.2013.2278332⟩ Article dans une revue hal-01743999v1
	Compact Modeling Solutions for Oxide-Based Resistive Switching Memories (OxRAM) Marc Bocquet , Hassen Aziza , Weisheng Zhao , Yue Zhang , Santhosh Onkaraiah Journal of Low Power Electronics and Applications, 2014, 4 (1), pp.1-14. ⟨10.3390/jlpea4010001⟩ Article dans une revue hal-01737320v1
	RRAM-based FPGA for “Normally Off, Instantly On” applications Ogun Turkyilmaz , Santhosh Onkaraiah , Marina Reyboz , Fabien Clermidy , H. Hraziia Journal of Parallel and Distributed Computing, 2014, 74, pp.2441 - 2451. ⟨10.1016/j.jpdc.2013.08.003⟩ Article dans une revue hal-01743243v1
	An Overview of Non-Volatile Flip-Flops Based on Emerging Memory Technologies Jean-Michel Portal , Marc Bocquet , Mathieu Moreau , Hassen Aziza , Damien Deleruyelle Journal of Electronic Science and Technology, 2014, 12 (2), pp.173 - 181. ⟨10.3969/j.issn.1674-862X.2014.02.007⟩ Article dans une revue hal-01745646v1
	Robust Compact Model for Bipolar Oxide-Based Resistive Switching Memories Marc Bocquet , Damien Deleruyelle , Hassen Aziza , Christophe Muller , Jean-Michel Portal IEEE Transactions on Electron Devices, 2014, 61 (3), pp.674 - 681. ⟨10.1109/TED.2013.2296793⟩ Article dans une revue hal-01737291v1
	A novel test structure for OxRRAM process variability evaluation Hassen Aziza , Marc Bocquet , Jean-Michel Portal , Mathieu Moreau , Christophe Muller Microelectronics Reliability, 2013, 53 (9-11), pp.1208 - 1212. ⟨10.1016/j.microrel.2013.07.012⟩ Article dans une revue hal-01745650v1
	Operation and stability analysis of bipolar OxRRAM-based Non-Volatile 8T2R SRAM as solution for information back-up H. Hraziia , Adam Makosiej , Giorgio Palma , Jean-Michel Portal , Marc Bocquet Solid-State Electronics, 2013, 90, pp.99-106. ⟨10.1016/j.sse.2013.02.045⟩ Article dans une revue hal-01744003v1
	Non-Volatile Flip-Flop Based on Unipolar ReRAM for Power-Down Applications Jean-Michel Portal , Marc Bocquet , Damien Deleruyelle , Christophe Muller Journal of Low Power Electronics, 2012, 8 (1), pp.1 - 10. ⟨10.1166/jolpe.2012.1172⟩ Article dans une revue hal-01745507v1
	Self-consistent physical modeling of set/reset operations in unipolar resistive-switching memories Marc Bocquet , Damien Deleruyelle , Christophe Muller , Jean-Michel Portal Applied Physics Letters, 2011, 98 (26), ⟨10.1063/1.3605591⟩ Article dans une revue hal-01779321v1

	A Multimode Hybrid Memristor-CMOS Prototyping Platform Supporting Digital and Analog Projects Kamel-Eddine Harabi , C. Turck , Marie Drouhin , A. Renaudineau , T. Bersani-Veroni 2023 28th Asia and South Pacific Design Automation Conference (ASP-DAC), Jan 2023, Tokyo (Japan), France. pp.184-185, ⟨10.1145/3566097.3567944⟩ Communication dans un congrès hal-04270420v1
	Binary ReRAM-based BNN first-layer implementation Mona Ezzadeen , Atreya Majumdar , Sigrid Thomas , Jean-Philippe Noël , Bastien Giraud 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), Apr 2023, Antwerp, Belgium. pp.1-6, ⟨10.23919/DATE56975.2023.10137057⟩ Communication dans un congrès hal-04270562v1
	Experimental Demonstration of Memristor Delay-Based Logic In-Memory Ternary Neural Network A. Renaudineau , K.-E. Harabi , C. Turck , A. Laborieux , E. Vianello 2023 Silicon Nanoelectronics Workshop (SNW), Jun 2023, Kyoto, Japan. pp.43-44, ⟨10.23919/SNW57900.2023.10183957⟩ Communication dans un congrès hal-04270396v1
	1S1R sub-threshold operation in Crossbar arrays for low power BNN inference computing J. Minguet Lopez , F. Rummens , L. Reganaz , A. Heraud , T. Hirtzlin IMW 2022 - IEEE International Memory Workshop, May 2022, Dresden, Germany. pp.1-4, ⟨10.1109/IMW52921.2022.9779253⟩ Communication dans un congrès cea-03707392v1
	Low-Overhead Implementation of Binarized Neural Networks Employing Robust 2T2R Resistive RAM Bridges M. Ezzadeen , A. Majumdar , Marc Bocquet , B. Giraud , J.-P. Noel ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC), Sep 2021, Grenoble, France. pp.83-86, ⟨10.1109/ESSCIRC53450.2021.9567742⟩ Communication dans un congrès hal-03597353v1
	CAPC: A Configurable Analog Pop-Count Circuit for Near-Memory Binary Neural Networks F. Jebali , A. Majumdar , A. Laborieux , T. Hirtzlin , E. Vianello 2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Aug 2021, Lansing, France. pp.158-161, ⟨10.1109/MWSCAS47672.2021.9531919⟩ Communication dans un congrès hal-03624922v1
	Ge-Se-Sb-N-based OTS scaling perspectives for high-density 1S1R crossbar arrays J. Minguet Lopez , N. Castellani , L. Grenouillet , L. Reganaz , G. Navarro 2021 IEEE INTERNATIONAL MEMORY WORKSHOP (IMW), May 2021, Dresde, Germany. pp.107-110, ⟨10.1109/IMW51353.2021.9439606⟩ Communication dans un congrès hal-03622145v1
	Low Power In-Memory Implementation of Ternary Neural Networks with Resistive RAM-Based Synapse Axel Laborieux , Marc Bocquet , Tifenn Hirtzlin , Jacques-Olivier Klein , L Herrera Diez 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2020, Genova (virtual), Italy. ⟨10.1109/AICAS48895.2020.9073877⟩ Communication dans un congrès hal-02403984v1
	Memory-Centric Neuromorphic Computing With Nanodevices Damien Querlioz , Tifenn Hirtzlin , Jacques-Olivier Klein , Etienne Nowak , Elisa Vianello Biomedical Circuits and Systems Conference (BiOCAS), Oct 2019, Nara, Japan. ⟨10.1109/BIOCAS.2019.8919010⟩ Communication dans un congrès hal-02399731v1
	Implementing Binarized Neural Networks with Magnetoresistive RAM without Error Correction Tifenn Hirtzlin , Bogdan Penkovsky , Jacques-Olivier Klein , Nicolas Locatelli , Adrien Vincent 15th IEEE / ACM International Symposium on Nanoscale Architectures (NANOARCH), Jul 2019, Qingdao, China Communication dans un congrès hal-02399718v1
	Outstanding Bit Error Tolerance of Resistive RAM-Based Binarized Neural Networks T Hirtzlin , Marc Bocquet , J.-O Klein , E. Nowak , E. Vianello IEEE International Conference on Artificial Intellignence Circuits and Systems (AICAS), Mar 2019, Hsinshu, Taiwan. ⟨10.1109/AICAS.2019.8771544⟩ Communication dans un congrès hal-02159142v1
	Resistive and spintronic RAMs: device, simulation, and applications Elena Ioana Vatajelu , Lorena Anghel , Jean-Michel Portal , Marc Bocquet , Guillaume Prenat IOLTS 2018 - IEEE 24th International Symposium on On-Line Testing And Robust System Design, Jul 2018, Platja d'Aro, Spain. pp.109-114, ⟨10.1109/IOLTS.2018.8474226⟩ Communication dans un congrès hal-01976583v1
	PCM compact model: Optimized methodology for model card extraction Corentin Pigot , Fabien Gilibert , Marina Reyboz , Marc Bocquet , Jean-Michel Portal 2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Sep 2018, Austin, United States. pp.190-193, ⟨10.1109/SISPAD.2018.8551654⟩ Communication dans un congrès cea-02188521v1
	In-Memory and Error-Immune Differential RRAM Implementation of Binarized Deep Neural Networks Marc Bocquet , T. Hirztlin , J.-O. Klein , E. Nowak , E. Vianello 2018 IEEE International Electron Devices Meeting (IEDM), Dec 2018, San Francisco, United States. pp.20.6.1-20.6.4, ⟨10.1109/IEDM.2018.8614639⟩ Communication dans un congrès hal-02011124v1
	Thermal Laser Attack and High Temperature Heating on HfO2-based OxRAM Cells A Krakovinsky , Marc Bocquet , R Wacquez , J. Coignus , Jean-Michel Portal International Symposium on On-Line Testing and Robust System Design, Jul 2017, Thessaloniki, Greece Communication dans un congrès hal-01737925v1
	ReRAM ON/OFF resistance ratio degradation due to line resistance combined with device variability in 28nm FDSOI technology Hassen Aziza , P. Canet , J. Postel-Pellerin , Mathieu Moreau , Jean-Michel Portal 2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), Apr 2017, Athens, Greece. ⟨10.1109/ULIS.2017.7962594⟩ Communication dans un congrès hal-01745666v1
	Continuous Multilevel Compact Model of Subthreshold Conduction and Threshold Switching in Phase-Change Memory Corentin Pigot , Fabien Gilibert , Marina Reyboz , Marc Bocquet , Paola Zuliani 49th International Conference on Solid State Devices and Materals, Sep 2017, Tsukuba, Japan Communication dans un congrès hal-01737914v1
	Functionality and reliability of resistive RAM (RRAM) for non-volatile memory applications G. Molas , G. Piccolboni , M. Barci , B. Traore , J. Guy 2016 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS AND APPLICATION (VLSI-TSA), 2016, Unknown, Unknown Region Communication dans un congrès hal-01435224v1
	Multilevel Operation in Oxide Based Resistive RAM with SET voltage modulation Hassen Aziza , H. Ayari , S. Onkaraiah , Mathieu Moreau , Jean-Michel Portal 2016 11TH IEEE INTERNATIONAL CONFERENCE ON DESIGN & TECHNOLOGY OF INTEGRATED SYSTEMS IN NANOSCALE ERA (DTIS), Apr 2016, Istanbul, Turkey. pp.1-5, ⟨10.1109/DTIS.2016.7483892⟩ Communication dans un congrès hal-01434981v1
	Impact of a Laser Pulse On HfO$_2$-based RRAM Cells Reliability and Integrity A. Krakovinsky , Marc Bocquet , R. Wacquez , J. Coignus , D. Deleruyelle 2016 INTERNATIONAL CONFERENCE ON MICROELECTRONIC TEST STRUCTURES (ICMTS), 2016, Unknown, Unknown Region. pp.152-156 Communication dans un congrès hal-01435097v1
	Oxide based resistive RAM: ON/OFF resistance analysis versus circuit variability Hassen Aziza , Haytem Ayari , Santhosh Onkaraiah , Jean-Michel Portal , Mathieu Moreau 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Oct 2014, Amsterdam, Netherlands. ⟨10.1109/DFT.2014.6962107⟩ Communication dans un congrès hal-01745718v1
	Resistive memories: Which applications? Fabien Clermidy , Natalija Jovanovic , Santhosh Onkaraiah , Houcine Oucheikh , Olivier Thomas Design Automation and Test in Europe, Mar 2014, Dresden, France. ⟨10.7873/DATE.2014.282⟩ Communication dans un congrès hal-01804664v1
	Printed complementary organic thin film transistors based decoder for ferroelectric memory A El Amraoui , Marc Bocquet , F. Barros , Jean-Michel Portal , M. Charbonneau ESSCIRC 2014 - 40th European Solid State Circuits Conference, Sep 2014, Venice Lido, France. ⟨10.1109/ESSCIRC.2014.6942034⟩ Communication dans un congrès hal-01738468v1
	SPICE level analysis of Single Event Effects in an OxRRAM cell K. Coulié , Marc Bocquet , Hassen Aziza , Jean-Michel Portal , Wenceslas Rahajandraibe 2013 14th Latin American Test Workshop - LATW, Apr 2013, Cordoba, France. ⟨10.1109/LATW.2013.6562684⟩ Communication dans un congrès hal-01804661v1
	Single-ended sense amplifier robustness evaluation for OxRRAM technology Hassen Aziza , Marc Bocquet , Mathieu Moreau , Jean-Michel Portal 2013 IEEE Design and Test Symposium (IDT), Dec 2013, Marrakesh, Morocco. ⟨10.1109/IDT.2013.6727097⟩ Communication dans un congrès hal-01745737v1
	Analytical study of complementary memristive synchronous logic gates Jean-Michel Portal , Mathieu Moreau , Marc Bocquet , Hassen Aziza , Damien Deleruyelle 2013 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), Jul 2013, Brooklyn, United States. ⟨10.1109/NanoArch.2013.6623047⟩ Communication dans un congrès hal-01745759v1
	A Built-In Self-Test Structure (BIST) for Resistive RAMs Characterization: Application to Bipolar OxRRAMs Hassen Aziza , Marc Bocquet , Mathieu Moreau , Jean-Michel Portal International Semiconductor Device Research Symposium, Dec 2013, Bethesda, United States Communication dans un congrès hal-01745729v1
	Synchronous Full-Adder based on Complementary Resistive Switching Memory Cells Y Zhang , Erya y Deng , Jacques-Olivier O Klein , Damien Querlioz , Dafiné Ravelosona 11th International New Circuits and Systems Conference (NEWCAS), Jun 2013, Paris, France. ⟨10.1109/NEWCAS.2013.6573578⟩ Communication dans un congrès hal-01840795v1
	Crossbar architecture based on 2R complementary resistive switching memory cell Weisheng Zhao , Y Zhang , Jacques-Olivier Klein , Damien S Querlioz , Dafine Ravelosona 2012 IEEE/ACM International Symposium on Nanoscale Architectures , Jul 2012, Amsterdam, Netherlands. ⟨10.1145/2765491.2765508⟩ Communication dans un congrès hal-01745351v1
	Bipolar ReRAM Based Non-‐Volatile Flip-‐flops for Low-‐Power Architectures Santhosh Onkaraiah , Marina Reyboz , Fabien Clermidy , Jean-Michel Portal , Marc Bocquet 2012 IEEE 10th International New Circuits and Systems Conference (NEWCAS), Jun 2012, Montreal, Canada. ⟨10.1109/NEWCAS.2012.6329045⟩ Communication dans un congrès hal-01745498v1
	Design challenges for prototypical and emerging memory concepts relying on resistance switching Christophe Muller , D. Deleruyelle , O. Ginez , Jean-Michel Portal , Marc Bocquet 2011 IEEE Custom Integrated Circuits Conference (CICC 2011), Sep 2011, San Jose, CA, United States. ⟨10.1109/CICC.2011.6055316⟩ Communication dans un congrès hal-01745644v1

Marc Bocquet

Présentation

Publications

Voltage-dependent synaptic plasticity: Unsupervised probabilistic Hebbian plasticity rule based on neurons membrane potential

Model of the Weak Reset Process in HfO x Resistive Memory for Deep Learning Frameworks

OxRAM+OTS optimization for Binarized Neural Network hardware implementation

Write Termination circuits for RRAM : A Holistic Approach From Technology to Application Considerations

Implementation of Ternary Weights With Resistive RAM Using a Single Sense Operation per Synapse

Digital Biologically Plausible Implementation of Binarized Neural Networks With Differential Hafnium Oxide Resistive Memory Arrays

Switching Event Detection and Self-Termination Programming Circuit for Energy Efficient ReRAM Memory Arrays

Stochastic Computing for Hardware Implementation of Binarized Neural Networks

Phase-Change Memory: A Continuous Multilevel Compact Model of Subthreshold Conduction and Threshold Switching

Comprehensive Phase-Change Memory Compact Model for Circuit Simulation

Design and Simulation of a 128 kb Embedded Nonvolatile Memory Based on a Hybrid RRAM (HfO$_2$ )/28 nm FDSOI CMOS Technology

A Built-In Self-Test Structure (BIST) for Resistive RAMs Characterization: Application to Bipolar OxRRAM

Synchronous Non-Volatile Logic Gate Design Based on Resistive Switching Memories

Compact Modeling Solutions for Oxide-Based Resistive Switching Memories (OxRAM)

RRAM-based FPGA for “Normally Off, Instantly On” applications

An Overview of Non-Volatile Flip-Flops Based on Emerging Memory Technologies

Robust Compact Model for Bipolar Oxide-Based Resistive Switching Memories

A novel test structure for OxRRAM process variability evaluation

Operation and stability analysis of bipolar OxRRAM-based Non-Volatile 8T2R SRAM as solution for information back-up

Non-Volatile Flip-Flop Based on Unipolar ReRAM for Power-Down Applications

Self-consistent physical modeling of set/reset operations in unipolar resistive-switching memories

A Multimode Hybrid Memristor-CMOS Prototyping Platform Supporting Digital and Analog Projects

Binary ReRAM-based BNN first-layer implementation

Experimental Demonstration of Memristor Delay-Based Logic In-Memory Ternary Neural Network

1S1R sub-threshold operation in Crossbar arrays for low power BNN inference computing

Low-Overhead Implementation of Binarized Neural Networks Employing Robust 2T2R Resistive RAM Bridges

CAPC: A Configurable Analog Pop-Count Circuit for Near-Memory Binary Neural Networks

Ge-Se-Sb-N-based OTS scaling perspectives for high-density 1S1R crossbar arrays

Low Power In-Memory Implementation of Ternary Neural Networks with Resistive RAM-Based Synapse

Memory-Centric Neuromorphic Computing With Nanodevices

Implementing Binarized Neural Networks with Magnetoresistive RAM without Error Correction

Outstanding Bit Error Tolerance of Resistive RAM-Based Binarized Neural Networks

Resistive and spintronic RAMs: device, simulation, and applications

PCM compact model: Optimized methodology for model card extraction

In-Memory and Error-Immune Differential RRAM Implementation of Binarized Deep Neural Networks

Thermal Laser Attack and High Temperature Heating on HfO2-based OxRAM Cells

ReRAM ON/OFF resistance ratio degradation due to line resistance combined with device variability in 28nm FDSOI technology

Continuous Multilevel Compact Model of Subthreshold Conduction and Threshold Switching in Phase-Change Memory

Functionality and reliability of resistive RAM (RRAM) for non-volatile memory applications

Multilevel Operation in Oxide Based Resistive RAM with SET voltage modulation

Impact of a Laser Pulse On HfO$_2$-based RRAM Cells Reliability and Integrity

Oxide based resistive RAM: ON/OFF resistance analysis versus circuit variability

Resistive memories: Which applications?

Printed complementary organic thin film transistors based decoder for ferroelectric memory

SPICE level analysis of Single Event Effects in an OxRRAM cell

Single-ended sense amplifier robustness evaluation for OxRRAM technology

Analytical study of complementary memristive synchronous logic gates

A Built-In Self-Test Structure (BIST) for Resistive RAMs Characterization: Application to Bipolar OxRRAMs

Synchronous Full-Adder based on Complementary Resistive Switching Memory Cells

Crossbar architecture based on 2R complementary resistive switching memory cell

Bipolar ReRAM Based Non-­‐Volatile Flip-­‐flops for Low-­‐Power Architectures

Design challenges for prototypical and emerging memory concepts relying on resistance switching

Bipolar ReRAM Based Non-‐Volatile Flip-‐flops for Low-‐Power Architectures