Marc Bocquet

Enseignant Chercheur (Professeur des universités) à l'université d'Aix-Marseille.

Documents

Présentation

Professeur des Universités - 63ème section CNU ============================================== Unités de rattachement actuelles -------------------------------- ### Laboratoire de recherche : Institut Matériaux Microélectronique Nanosciences de Provence (Im2np) Im2np, UMR CNRS 7334 et Université d'Aix-Marseille <http://www.im2np.fr> Equipe Mémoires - Département ASCE ### Composante d'enseignement : IUT dpt GEII de Marseille <https://iut.univ-amu.fr/departements/geii-marseille> Responsabilités Administratives ### Laboratoire - Depuis 2017 : Co-responsable de l'équipe Mémoires de l'IM2NP - Depuis 2017 : Membre du conseil scientifique de l'IM2NP ### Unité de Formation - 2019-2020 : Co-responsable de la 2ème année du cycle préparatoire intégrée de Polytech Marseille - 2014-2019 : Responsable d'année du département MT de Polytech Marseille - 2012-2014 : Responsable d'un parcours d'enseignement au département MT de Polytech Marseille Diplômes -------- - Juin 2017 : Habilitation à diriger les recherches (HDR), Université d’Aix-Marseille. - Novembre 2009 : Thèse de doctorat en Micro&NanoElectronique de l'INPG, Grenoble. - 2005-2006 : Master NanoTechnologies Université Joseph Fourier, Grenoble, mention bien - 2003-2006 : Diplôme d'ingénieur ENSERG - INPG, Grenoble, mention très bien Activité d'enseignement ----------------------- Volume : Environ 2500 HETD enseignées depuis 2006 Niveaux : Cycle préparatoire (2A), école d'ingénieur (3A-4A-5A), formation continue Matières enseignés : Base de l'électronique numérique, microcontrôleur, électrotechnique, physique et technologie des composants à semi-conducteur, mémoires non-volatiles Thématiques de recherche ------------------------ ### Mots-clefs thématiques : Technologies mémoires émergentes, micro-nanoélectronique, électronique flexible, mémoires non-volatiles, mémoires résistives, RRAM, CBRAM, PCM, FRAM ### Compétences : Microscopie champ proche (AFM, EFM, KPFM, C-AFM), caractérisation électrique sous pointes, modélisation physique, modélisation compacte ### Thèmes : - Modélisation et caractérisation des mémoires innovantes : RRAM, PCRAM, FRAM - Développement technologique de dispositifs mémoires sur support souple\\\\ - Optimisation de nouvelles architectures mémoires de type EEPROM/Flash Projets de recherche -------------------- Implication en tant que participant (P) ou coordinateur (C) : - ANR Neuronic (2019-2023) (C) - IPCEI Nano2022 (2019-2022) (C) - UNICO Chist-ERA (2019-2022) (P) - ANR Reflex (2012-2015) (P) - ANR Dipmem (2012-2015) (P) - Carnot POLYMEM (2014) (P) Expertises Nationales --------------------- - Participation à des jurys de thèse : 2 en tant que président, 4 en tant que rapporteur et 1 en tant que Examinateur - Depuis 2016 : Expertise de dossiers AGIR-PEPS, ANR, IRS, projet region. - 2013 : Membre de la commission de Spécialité de la 63ème section collège B Encadrement doctoral -------------------- - 4 thèses en co-encadrement soutenues - 2 thèses en co-encadrement en cours. - Co-encadrement de thèses sous contrat CIFRE et CTBU CEA. Dissémination scientifique -------------------------- - 105 publications - 25 revues internationales à comité de lecture. - 54 proceedings de conférences internationales à comité de lecture. - 2 articles de vulgarisation scientifiques. - 7 conférences invitées - 1 brevet.

Publications

damien-querlioz

	A Memristor-Based Bayesian Machine Kamel-Eddine Harabi , Tifenn Hirtzlin , Clément Turck , Elisa Vianello , Raphaël Laurent Nature Electronics, 2023, 6, pp.52. ⟨10.1038/s41928-022-00886-9⟩ Article dans une revue hal-03861134v1
	Voltage-dependent synaptic plasticity: Unsupervised probabilistic Hebbian plasticity rule based on neurons membrane potential Nikhil Garg , Ismael Balafrej , Terrence Stewart , Jean-Michel Portal , Marc Bocquet Frontiers in Neuroscience, 2022, 16, 983950, 12 p. ⟨10.3389/fnins.2022.983950⟩ Article dans une revue hal-03834905v1
	Model of the Weak Reset Process in HfO x Resistive Memory for Deep Learning Frameworks Atreya Majumdar , Marc Bocquet , Tifenn Hirtzlin , Axel Laborieux , Jacques-Olivier Klein IEEE Transactions on Electron Devices, 2021, 68 (10), pp.4925-4932. ⟨10.1109/TED.2021.3108479⟩ Article dans une revue hal-03372056v1
	Digital Biologically Plausible Implementation of Binarized Neural Networks With Differential Hafnium Oxide Resistive Memory Arrays Tifenn Hirtzlin , Marc Bocquet , Bogdan Penkovsky , Jacques-Olivier Klein , Etienne Nowak Frontiers in Neuroscience, 2020, 13, ⟨10.3389/fnins.2019.01383⟩ Article dans une revue hal-02436382v1
	Implementation of Ternary Weights With Resistive RAM Using a Single Sense Operation per Synapse Axel Laborieux , Marc Bocquet , Hirtzlin Tifenn , Jacques-Olivier Klein , Etienne Nowak IEEE Transactions on Circuits and Systems I: Regular Papers, 2020, pp.1-10. ⟨10.1109/TCSI.2020.3031627⟩ Article dans une revue hal-02983778v1
	Stochastic Computing for Hardware Implementation of Binarized Neural Networks Tifenn Hirtzlin , Bogdan Penkovsky , Marc Bocquet , Jacques-Olivier Klein , Jean-Michel Portal IEEE Access, 2019, pp.1-1. ⟨10.1109/ACCESS.2019.2921104⟩ Article dans une revue hal-02158846v1
	Synchronous Non-Volatile Logic Gate Design Based on Resistive Switching Memories Weisheng Zhao , Mathieu Moreau , Erya Deng , Yue Zhang , Jean-Michel Portal IEEE Transactions on Circuits and Systems I: Regular Papers, 2014, 61 (2), pp.443 - 454. ⟨10.1109/TCSI.2013.2278332⟩ Article dans une revue hal-01743999v1
	Design and analysis of crossbar architecture based on complementary resistive switching non-volatile memory cells W. Zhao , M. Portal , W. Kang , Mathieu Moreau , Y. Zhang Journal of Parallel and Distributed Computing, 2014, 74 (6), pp.2484 - 2496. ⟨10.1016/j.jpdc.2013.08.004⟩ Article dans une revue hal-01744000v1

	Binary ReRAM-based BNN first-layer implementation Mona Ezzadeen , Atreya Majumdar , Sigrid Thomas , Jean-Philippe Noël , Bastien Giraud 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), Apr 2023, Antwerp, Belgium. pp.1-6, ⟨10.23919/DATE56975.2023.10137057⟩ Communication dans un congrès hal-04270562v1
	Experimental Demonstration of Memristor Delay-Based Logic In-Memory Ternary Neural Network A. Renaudineau , K.-E. Harabi , C. Turck , A. Laborieux , E. Vianello 2023 Silicon Nanoelectronics Workshop (SNW), Jun 2023, Kyoto, Japan. pp.43-44, ⟨10.23919/SNW57900.2023.10183957⟩ Communication dans un congrès hal-04270396v1
	A Multimode Hybrid Memristor-CMOS Prototyping Platform Supporting Digital and Analog Projects Kamel-Eddine Harabi , C. Turck , Marie Drouhin , A. Renaudineau , T. Bersani-Veroni 2023 28th Asia and South Pacific Design Automation Conference (ASP-DAC), Jan 2023, Tokyo (Japan), France. pp.184-185, ⟨10.1145/3566097.3567944⟩ Communication dans un congrès hal-04270420v1
	Low-Overhead Implementation of Binarized Neural Networks Employing Robust 2T2R Resistive RAM Bridges M. Ezzadeen , A. Majumdar , Marc Bocquet , B. Giraud , J.-P. Noel ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC), Sep 2021, Grenoble, France. pp.83-86, ⟨10.1109/ESSCIRC53450.2021.9567742⟩ Communication dans un congrès hal-03597353v1
	CAPC: A Configurable Analog Pop-Count Circuit for Near-Memory Binary Neural Networks F. Jebali , A. Majumdar , A. Laborieux , T. Hirtzlin , E. Vianello 2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Aug 2021, Lansing, France. pp.158-161, ⟨10.1109/MWSCAS47672.2021.9531919⟩ Communication dans un congrès hal-03624922v1
	High-Density 3D Monolithically Integrated Multiple 1T1R Multi-Level-Cell for Neural Networks E. Esmanhotto , L. Brunet , N. Castellani , D. Bonnet , T. Dalgaty 2020 IEEE International Electron Devices Meeting (IEDM), Dec 2020, San Francisco (virtual), United States. pp.36.5.1-36.5.4, ⟨10.1109/IEDM13553.2020.9372019⟩ Communication dans un congrès hal-03218937v1
	In-Memory Resistive RAM Implementation of Binarized Neural Networks for Medical Applications Bogdan Penkovsky , Marc Bocquet , Tifenn Hirtzlin , Jacques-Olivier Klein , Etienne Nowak 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), Mar 2020, Grenoble, France. pp.690-695, ⟨10.23919/DATE48585.2020.9116439⟩ Communication dans un congrès hal-03218970v1
	Low Power In-Memory Implementation of Ternary Neural Networks with Resistive RAM-Based Synapse Axel Laborieux , Marc Bocquet , Tifenn Hirtzlin , Jacques-Olivier Klein , L Herrera Diez 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2020, Genova (virtual), Italy. ⟨10.1109/AICAS48895.2020.9073877⟩ Communication dans un congrès hal-02403984v1
	Embracing the unreliability of memory devices for neuromorphic computing Marc Bocquet , Tifenn Hirtzlin , Jacques-Olivier Klein , Etienne Nowak , Elisa Vianello IRPS 2020 - IEEE International Reliability Physics Symposium, IEEE, Apr 2020, Dallas (Texas), United States. pp.1-5, ⟨10.1109/IRPS45951.2020.9128346⟩ Communication dans un congrès hal-04019222v1
	Hybrid Analog-Digital Learning with Differential RRAM Synapses T. Hirtzlin , Marc Bocquet , M. Ernoult , J.-O Klein , E. Nowak 2019 IEEE International Electron Devices Meeting (IEDM), Dec 2019, San Francisco, United States. ⟨10.1109/IEDM19573.2019.8993555⟩ Communication dans un congrès hal-02399624v1
	Implementing Binarized Neural Networks with Magnetoresistive RAM without Error Correction Tifenn Hirtzlin , Bogdan Penkovsky , Jacques-Olivier Klein , Nicolas Locatelli , Adrien Vincent 15th IEEE / ACM International Symposium on Nanoscale Architectures (NANOARCH), Jul 2019, Qingdao, China Communication dans un congrès hal-02399718v1
	Outstanding Bit Error Tolerance of Resistive RAM-Based Binarized Neural Networks T Hirtzlin , Marc Bocquet , J.-O Klein , E. Nowak , E. Vianello IEEE International Conference on Artificial Intellignence Circuits and Systems (AICAS), Mar 2019, Hsinshu, Taiwan. ⟨10.1109/AICAS.2019.8771544⟩ Communication dans un congrès hal-02159142v1
	Memory-Centric Neuromorphic Computing With Nanodevices Damien Querlioz , Tifenn Hirtzlin , Jacques-Olivier Klein , Etienne Nowak , Elisa Vianello Biomedical Circuits and Systems Conference (BiOCAS), Oct 2019, Nara, Japan. ⟨10.1109/BIOCAS.2019.8919010⟩ Communication dans un congrès hal-02399731v1
	In-Memory and Error-Immune Differential RRAM Implementation of Binarized Deep Neural Networks Marc Bocquet , T. Hirztlin , J.-O. Klein , E. Nowak , E. Vianello 2018 IEEE International Electron Devices Meeting (IEDM), Dec 2018, San Francisco, United States. pp.20.6.1-20.6.4, ⟨10.1109/IEDM.2018.8614639⟩ Communication dans un congrès hal-02011124v1
	Analytical study of complementary memristive synchronous logic gates Jean-Michel Portal , Mathieu Moreau , Marc Bocquet , Hassen Aziza , Damien Deleruyelle 2013 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), Jul 2013, Brooklyn, United States. ⟨10.1109/NanoArch.2013.6623047⟩ Communication dans un congrès hal-01745759v1
	Synchronous Full-Adder based on Complementary Resistive Switching Memory Cells Y Zhang , Erya y Deng , Jacques-Olivier O Klein , Damien Querlioz , Dafiné Ravelosona 11th International New Circuits and Systems Conference (NEWCAS), Jun 2013, Paris, France. ⟨10.1109/NEWCAS.2013.6573578⟩ Communication dans un congrès hal-01840795v1
	Crossbar architecture based on 2R complementary resistive switching memory cell Weisheng Zhao , Y Zhang , Jacques-Olivier Klein , Damien S Querlioz , Dafine Ravelosona 2012 IEEE/ACM International Symposium on Nanoscale Architectures , Jul 2012, Amsterdam, Netherlands. ⟨10.1145/2765491.2765508⟩ Communication dans un congrès hal-01745351v1

Marc Bocquet

Présentation

Publications

A Memristor-Based Bayesian Machine

Voltage-dependent synaptic plasticity: Unsupervised probabilistic Hebbian plasticity rule based on neurons membrane potential

Model of the Weak Reset Process in HfO x Resistive Memory for Deep Learning Frameworks

Digital Biologically Plausible Implementation of Binarized Neural Networks With Differential Hafnium Oxide Resistive Memory Arrays

Implementation of Ternary Weights With Resistive RAM Using a Single Sense Operation per Synapse

Stochastic Computing for Hardware Implementation of Binarized Neural Networks

Synchronous Non-Volatile Logic Gate Design Based on Resistive Switching Memories

Design and analysis of crossbar architecture based on complementary resistive switching non-volatile memory cells

Binary ReRAM-based BNN first-layer implementation

Experimental Demonstration of Memristor Delay-Based Logic In-Memory Ternary Neural Network

A Multimode Hybrid Memristor-CMOS Prototyping Platform Supporting Digital and Analog Projects

Low-Overhead Implementation of Binarized Neural Networks Employing Robust 2T2R Resistive RAM Bridges

CAPC: A Configurable Analog Pop-Count Circuit for Near-Memory Binary Neural Networks

High-Density 3D Monolithically Integrated Multiple 1T1R Multi-Level-Cell for Neural Networks

In-Memory Resistive RAM Implementation of Binarized Neural Networks for Medical Applications

Low Power In-Memory Implementation of Ternary Neural Networks with Resistive RAM-Based Synapse

Embracing the unreliability of memory devices for neuromorphic computing

Hybrid Analog-Digital Learning with Differential RRAM Synapses

Implementing Binarized Neural Networks with Magnetoresistive RAM without Error Correction

Outstanding Bit Error Tolerance of Resistive RAM-Based Binarized Neural Networks

Memory-Centric Neuromorphic Computing With Nanodevices

In-Memory and Error-Immune Differential RRAM Implementation of Binarized Deep Neural Networks

Analytical study of complementary memristive synchronous logic gates

Synchronous Full-Adder based on Complementary Resistive Switching Memory Cells

Crossbar architecture based on 2R complementary resistive switching memory cell