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Arnaud Virazel

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Présentation

Enseignant-chercheur au **LIRMM** dans l’équipe de recherche **TEST**: Test and dEpendability of microelectronic integrated SysTems. <https://www.lirmm.fr/recherche/equipes/test> **Cours** : <http://www.lirmm.fr/~virazel/COURS/index.php?dir=L1%20-%20HLEE202/Cours/> **Researchgate** : [https://www.researchgate.net/profile/Arnaud\_Virazel](https://www.researchgate.net/profile/Arnaud_Virazel)

Publications

990392
"luigi-dilillo"

Scan-chain intra-cell defects grading

Aymen Touati , Alberto Bosio , Luigi Dilillo , Patrick Girard , Arnaud Virazel
DTIS: Design and Technology of Integrated Systems in Nanoscale Era, Apr 2015, Naples, Italy. ⟨10.1109/DTIS.2015.7127349⟩
Communication dans un congrès lirmm-01272696v1
Image document

Exploring the impact of functional test programs re-used for power-aware testing

Aymen Touati , Alberto Bosio , Luigi Dilillo , Patrick Girard , Arnaud Virazel
DATE 2015 - 18th Design, Automation and Test in Europe Conference and Exhibition, Mar 2015, Grenoble, France. pp.1277-1280, ⟨10.7873/DATE.2015.1031⟩
Communication dans un congrès lirmm-01272937v1

An effective ATPG flow for Gate Delay Faults

Alberto Bosio , Luigi Dilillo , Patrick Girard , Arnaud Virazel , Paolo Bernardi
DTIS: Design and Technology of Integrated Systems in Nanoscale Era, Apr 2015, Naples, Italy. ⟨10.1109/DTIS.2015.7127350⟩
Communication dans un congrès lirmm-01272719v1

A Functional Power Evaluation Flow for Defining Test Power Limits during At-Speed Delay Testing

Miroslav Valka , Alberto Bosio , Luigi Dilillo , Patrick Girard , Serge Pravossoudovitch
ETS 2011 - 16th IEEE European Test Symposium, May 2011, Trondheim, Norway. pp.153-158, ⟨10.1109/ETS.2011.21⟩
Communication dans un congrès lirmm-00647822v1