Accéder directement au contenu

Arnaud Virazel

33%
Libre accès
3
Documents
Affiliations actuelles
  • 1100642
Identifiants chercheurs
Contact

Présentation

Enseignant-chercheur au **LIRMM** dans l’équipe de recherche **TEST**: Test and dEpendability of microelectronic integrated SysTems. <https://www.lirmm.fr/recherche/equipes/test> **Cours** : <http://www.lirmm.fr/~virazel/COURS/index.php?dir=L1%20-%20HLEE202/Cours/> **Researchgate** : [https://www.researchgate.net/profile/Arnaud\_Virazel](https://www.researchgate.net/profile/Arnaud_Virazel)

Publications

982385

Analysis of Setup & Hold Margins Inside Silicon for Advanced Technology Nodes

Deepak Kumar Arora , Darayus Adil Patel , Nc Shahabuddin , Sanjay Kumar , Navin Kumar Dayani
ISQED 2016 - 17th International Symposium on Quality Electronic Design, Mar 2016, Santa Clara, CA, United States. pp.295-300, ⟨10.1109/ISQED.2016.7479217⟩
Communication dans un congrès lirmm-01433314v1
Image document

Design and performance parameters of an ultra-low voltage, single supply 32bit processor implemented in 28nm FDSOI technology

Sylvain Clerc , Fady Abouzeid , Darayus Adil Patel , Jean-Marc Daveau , Cyril Bottoni
ISQED 2015 - 16th International Symposium on Quality Electronic Design, Apr 2015, Santa Clara, United States. pp.366-370, ⟨10.1109/ISQED.2015.7085453⟩
Communication dans un congrès lirmm-01272913v1