Arnaud Virazel
30%
Libre accès
10
Documents
Affiliations actuelles
- 1100642
Identifiants chercheurs
arnaud-virazel- IdRef : 068454724
- ISNI : 0000000139422532
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0000-0001-7398-7107
Présentation
Enseignant-chercheur au **LIRMM** dans l’équipe de recherche **TEST**: Test and dEpendability of microelectronic integrated SysTems.
<https://www.lirmm.fr/recherche/equipes/test>
**Cours** :
<http://www.lirmm.fr/~virazel/COURS/index.php?dir=L1%20-%20HLEE202/Cours/>
**Researchgate** :
[https://www.researchgate.net/profile/Arnaud\_Virazel](https://www.researchgate.net/profile/Arnaud_Virazel)
Publications
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A Low-Cost Reliability vs. Cost Trade-Off Methodology to Selectively Harden Logic CircuitsJournal of Electronic Testing: : Theory and Applications, 2017, 33 (1), pp.25-36. ⟨10.1007/s10836-017-5640-6⟩
Article dans une revue
lirmm-01718568v1
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A Hybrid Fault-Tolerant Architecture for Highly Reliable Processing CoresJournal of Electronic Testing: : Theory and Applications, 2016, 32 (2), pp.147-161. ⟨10.1007/s10836-016-5578-0⟩
Article dans une revue
lirmm-01354746v1
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Can we Approximate the Test of Integrated Circuits?WAPCO: Workshop On Approximate Computing, Jan 2017, Stockholm, Sweden
Communication dans un congrès
lirmm-02004418v1
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Towards approximation during test of Integrated CircuitsDDECS 2017 - 20th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Apr 2017, Dresden, Germany. pp.28-33, ⟨10.1109/DDECS.2017.7934574⟩
Communication dans un congrès
lirmm-01718580v1
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A Low-Cost Reliability vs. Cost Trade-Off Methodology to Selectively Harden Logic CircuitsETS: European Test Symposium, May 2016, Amsterdam, Netherlands. ⟨10.1109/ETS.2016.7519296⟩
Communication dans un congrès
hal-01444734v1
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A Case Study on the Approximate Test of Integrated CircuitsAC: Approximate Computing, Oct 2016, Pittsburgh, PA, United States
Communication dans un congrès
lirmm-01718609v1
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Design space exploration and optimization of a Hybrid Fault-Tolerant ArchitectureIOLTS: International On-Line Testing Symposium, Jul 2015, Halkidiki, Greece. pp.89-94, ⟨10.1109/IOLTS.2015.7229838⟩
Communication dans un congrès
lirmm-01272735v1
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An effective hybrid fault-tolerant architecture for pipelined coresETS: European Test Symposium, May 2015, Cluj-Napoca, Romania. ⟨10.1109/ETS.2015.7138733⟩
Communication dans un congrès
lirmm-01272730v1
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An Experimental Comparative Study of Fault-Tolerant ArchitecturesVALID: Advances in System Testing and Validation Lifecycle, Nov 2015, Barcelone, Spain. pp.1-6
Communication dans un congrès
lirmm-01354754v1
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Protecting combinational logic in pipelined microprocessor cores against transient and permanent faultsDDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2014, Warsaw, Poland. pp.223-225, ⟨10.1109/DDECS.2014.6868794⟩
Communication dans un congrès
lirmm-01248598v1
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