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Arnaud Virazel


Enseignant-chercheur au LIRMM dans l’équipe de recherche TEST: Test and dEpendability of microelectronic integrated SysTems.

https://www.lirmm.fr/recherche/equipes/test

Cours :

http://www.lirmm.fr/~virazel/COURS/index.php?dir=L1%20-%20HLEE202/Cours/

Researchgate :

https://www.researchgate.net/profile/Arnaud_Virazel


Article dans une revue41 documents

  • Arnaud Virazel, Imran Wali, Bastien Deveautour, Alberto Bosio, Patrick Girard, et al.. A Low-Cost Reliability vs. Cost Trade-Off Methodology to Selectively Harden Logic Circuits. Journal of Electronic Testing, Springer Verlag, 2017, 33 (1), pp.25-36. 〈10.1007/s10836-017-5640-6〉. 〈lirmm-01718568〉
  • Arnaud Virazel, Alejandro Nocua, Alberto Bosio, Patrick Girard, Cyril Chevalier. HPET: An Efficient Hybrid Power Estimation Technique to Improve High-Level Power Characterization. Journal of Circuits, Systems, and Computers, World Scientific Publishing, 2017, 26 (08), 〈10.1142/S0218126617400047〉. 〈lirmm-01718575〉
  • Aymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi. Microprocessor Testing: Functional Meets Structural Test. Journal of Circuits, Systems, and Computers, World Scientific Publishing, 2017, 26 (08), 〈10.1142/S0218126617400072〉. 〈lirmm-01718578〉
  • Alejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard, Cyril Chevalier. A Cross-Level Power Estimation Technique to Improve IP Power Models Quality. Journal of Low Power Electronics, American Scientific Publishers, 2017, 13 (1), pp.10-28. 〈10.1166/jolpe.2017.1472〉. 〈lirmm-01433322〉
  • Aymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel, Matteo Sonza Reorda, et al.. Scan-Chain Intra-Cell Aware Testing. IEEE Transactions on Emerging Topics in Computing, Institute of Electrical and Electronics Engineers, 2016, PP (99), In press. 〈10.1109/TETC.2016.2624311〉. 〈lirmm-01430859〉
  • Kapil Juneja, Darayus Adil Patel, Rajesh Kumar Immadi, Balwant Singh, Sylvie Naudet, et al.. An Effective Power-Aware At-Speed Test Methodology for IP Qualification and Characterization. Journal of Electronic Testing, Springer Verlag, 2016, 32 (6), pp.721-733. 〈10.1007/s10836-016-5621-1〉. 〈lirmm-01446887〉
  • Imran Wali, Arnaud Virazel, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, et al.. A Hybrid Fault-Tolerant Architecture for Highly Reliable Processing Cores. Journal of Electronic Testing, Springer Verlag, 2016, 32 (2), pp.147-161. 〈10.1007/s10836-016-5578-0〉. 〈lirmm-01354746〉
  • Miroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, et al.. Design for Test and Diagnosis of Power Switches. Journal of Circuits, Systems, and Computers, World Scientific Publishing, 2016, 25 (3), pp.1640013. 〈10.1142/S0218126616400132〉. 〈lirmm-01272986〉
  • Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, et al.. Evaluating a Radiation Monitor for Mixed-Field Environments based on SRAM Technology. Journal of Instrumentation, IOP Publishing, 2014, 9, 〈10.1088/1748-0221/9/05/C05052〉. 〈lirmm-01234448〉
  • Zhenzhou Sun, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, et al.. Intra-Cell Defects Diagnosis. Journal of Electronic Testing, Springer Verlag, 2014, 30 (5), pp.541-555. 〈10.1007/s10836-014-5481-5〉. 〈lirmm-01272964〉
  • Ahn Duc Tran, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, et al.. A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and Systems. Journal of Electronic Testing, Springer Verlag, 2014, 30 (4), pp.401-413. 〈10.1007/s10836-014-5459-3〉. 〈lirmm-01272958〉
  • Leonardo Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, et al.. On the Test and Mitigation of Malfunctions in Low-Power SRAMs. Journal of Electronic Testing, Springer Verlag, 2014, 30 (5), pp.611-627. 〈http://link.springer.com/article/10.1007%2Fs10836-014-5479-z〉. 〈10.1007/s10836-014-5479-z〉. 〈lirmm-01238443〉
  • João Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, et al.. Dynamic Compact Model of Self-Referenced Magnetic Tunnel Junction. IEEE Transactions on Electron Devices, Institute of Electrical and Electronics Engineers, 2014, 61 (11), pp.3877-3882. 〈10.1109/TED.2014.2355418〉. 〈lirmm-01272978〉
  • Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, et al.. Multiple Cell Upset Classification in Commercial SRAMs. IEEE Transactions on Nuclear Science, Institute of Electrical and Electronics Engineers, 2014, 61 (4), pp.1747-1754. 〈http://ieeexplore.ieee.org/Xplore/home.jsp〉. 〈10.1109/TNS.2014.2313742〉. 〈lirmm-01234446〉
  • Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, et al.. An SRAM Based Monitor for Mixed-Field Radiation Environments. IEEE Transactions on Nuclear Science, Institute of Electrical and Electronics Engineers, 2014, 61 (4), pp.1663-1670. 〈http://ieeexplore.ieee.org/Xplore/home.jsp〉. 〈10.1109/TNS.2014.2299733〉. 〈lirmm-01234441〉
  • Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, et al.. 90 nm SRAM Static and Dynamic Mode Real-Time Testing at Concordia Station in Antarctica. IEEE Transactions on Nuclear Science, Institute of Electrical and Electronics Engineers, 2014, 61 (6), pp.3389-3394. 〈http://ieeexplore.ieee.org/Xplore/home.jsp〉. 〈10.1109/TNS.2014.2363120〉. 〈lirmm-01234455〉
  • Georgios Tsiligiannis, Luigi Dilillo, Viyas Gupta, Alberto Bosio, Patrick Girard, et al.. Dynamic Test Methods for COTS SRAMs. IEEE Transactions on Nuclear Science, Institute of Electrical and Electronics Engineers, 2014, 61 (6), pp.3095-3102. 〈http://ieeexplore.ieee.org/Xplore/home.jsp〉. 〈10.1109/TNS.2014.2363123〉. 〈lirmm-01234463〉
  • João Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, et al.. A Complete Resistive-Open Defect Analysis for Thermally Assisted Switching MRAMs. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE, 2014, 22 (11), pp.2326-2335. 〈10.1109/TVLSI.2013.2294080〉. 〈lirmm-01248578〉
  • Aida Todri-Sanial, Sandip Kundu, Patrick Girard, Alberto Bosio, Luigi Dilillo, et al.. Globally Constrained Locally Optimized 3-D Power Delivery Networks. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE, 2014, 22 (10), pp.2131-2144. 〈10.1109/TVLSI.2013.2283800〉. 〈lirmm-01255754〉
  • Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel. Uncorrelated Power Supply Noise and Ground Bounce Consideration for Test Pattern Generation. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE, 2013, 21 (5), pp.958-970. 〈10.1109/TVLSI.2012.2197427〉. 〈lirmm-00806774〉
  • Aida Todri-Sanial, Sandip Kundu, Patrick Girard, Alberto Bosio, Luigi Dilillo, et al.. A Study of Tapered 3-D TSVs for Power and Thermal Integrity. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE, 2013, 21 (2), pp.306-319. 〈10.1109/TVLSI.2012.2187081〉. 〈lirmm-00806776〉
  • Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Aida Todri-Sanial, et al.. Testing a Commercial MRAM under Neutron and Alpha Radiation in Dynamic Mode. IEEE Transactions on Nuclear Science, Institute of Electrical and Electronics Engineers, 2013, 60 (4), pp.2617-2622. 〈10.1109/TNS.2013.2239311〉. 〈lirmm-00805005〉
  • Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, et al.. Impact of Resistive-Bridging Defects in SRAM at Different Technology Nodes. Journal of Electronic Testing, Springer Verlag, 2012, 28 (3), pp.317-329. 〈http://link.springer.com/article/10.1007%2Fs10836-012-5291-6〉. 〈10.1007/s10836-012-5291-6〉. 〈lirmm-00805017〉
  • Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, et al.. Analysis and Fault Modeling of Actual Resistive Defects in ATMELtm eFlash Memories. Journal of Electronic Testing, Springer Verlag, 2012, 28 (2), pp.215-228. 〈lirmm-00806773〉
  • Julien Vial, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, et al.. SoC Yield Improvement - Using TMR Architectures for Manufacturing Defect Tolerance in Logic Cores. International Journal On Advances in Systems and Measurements, IARIA, 2010, 3 (1/2), pp.1-10. 〈lirmm-00553567〉
  • Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, et al.. A Comprehensive Analysis of Transition Fault Coverage and Test Power Dissipation for LOS and LOC Schemes. Journal of Low Power Electronics, American Scientific Publishers, 2010, 6 (2), pp.359-374. 〈lirmm-00553548〉
  • Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel. A Comprehensive Framework for Logic Diagnosis of Arbitrary Defects. IEEE Transactions on Computers, Institute of Electrical and Electronics Engineers, 2010, 59 (3), pp.289-300. 〈lirmm-00553545〉
  • Olivier Ginez, Jean-Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, et al.. Electrical Simulation Model of the 2T-FLOTOX Core-Cell for Defect Injection and Faulty Behaviour Prediction in eFlash. Journal of Electronic Testing, Springer Verlag, 2009, N/A, pp.127-144. 〈lirmm-00371370〉
  • Julien Vial, Arnaud Virazel, Alberto Bosio, Patrick Girard, Christian Landrault, et al.. Is TMR Suitable for Yield Improvement ?. IET Computers & Digital Techniques, Institution of Engineering and Technology, 2009, 3 (6), pp.581-592. 〈lirmm-00406961〉
  • Alexandre Ney, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian. Analysis of Resistive-Open Defects in SRAM Sense Amplifiers. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE, 2009, 17 (10), pp.1556-1559. 〈lirmm-00371367〉
  • Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, et al.. New March Elements for Address Decoder Open and Resistive Open Fault Detection in SRAM Memories. Journal of Integrated Circuits and Systems, Brazilian Microelectronics Society, 2008, 3 (1), pp.7-12. 〈lirmm-00341793〉
  • Nabil Badereddine, Zhanglei Wang, Patrick Girard, Krishnendu Chakrabarty, Arnaud Virazel, et al.. A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction. Journal of Electronic Testing, Springer Verlag, 2008, 24 (4), pp.353-364. 〈10.1007/s10836-007-5053-z〉. 〈lirmm-00331296〉
  • Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian. Analysis and Test of Resistive-Open Defects in SRAM Pre-Charge Circuits. Journal of Electronic Testing, Springer Verlag, 2007, 23 (3), pp.435-444. 〈lirmm-00194254〉
  • Christian Landrault, Yannick Bonhomme, Arnaud Virazel, Patrick Girard, Lois Guiller, et al.. A Gated Clock Scheme for Low Power Testing of Logic Cores. Journal of Electronic Testing, Springer Verlag, 2006, 22 (1), pp.89-99. 〈lirmm-00134766〉
  • Patrick Girard, Luigi Dilillo, Serge Pravossoudovitch, Arnaud Virazel, Magali Hage-Hassan, et al.. ADOFs and Resistive-ADOFs in SRAM Address Decoders: Test Conditions and March Solutions. Journal of Electronic Testing, Springer Verlag, 2006, 22 (3), pp.287-296. 〈lirmm-00134769〉
  • Simone Borri, Magali Hage-Hassan, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, et al.. Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test. Journal of Electronic Testing, Springer Verlag, 2005, 21 (2), pp.169-179. 〈10.1007/s10836-005-6146-1〉. 〈lirmm-00105313〉
  • Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, et al.. Efficient March Test Procedure for Dynamic Read Destructive Fault Detection in SRAM Memories. Journal of Electronic Testing, Springer Verlag, 2005, 21 (5), pp.551-561. 〈10.1007/s10836-005-1169-1〉. 〈lirmm-00105314〉
  • Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Hans-Joachim Wunderlich. High Defect Coverage with Low Power Test Sequences in a BIST Environment. IEEE Design & Test, IEEE, 2002, 19 (5), pp.44-52. 〈lirmm-00268585〉
  • R. David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel. Hardware Generation of Random Single Input Change Test Sequence. Journal of Electronic Testing, Springer Verlag, 2002, 18 (2), pp.145-157. 〈lirmm-00268540〉
  • Arnaud Virazel, René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch. Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences. Journal of Electronic Testing, Springer Verlag, 2001, 17 (3/4), pp.233-241. 〈lirmm-00345796〉
  • Patrick Girard, Christian Landrault, Véronique Moreda, Serge Pravossoudovitch, Arnaud Virazel. A Scan-BIST Structure to Test Delay Faults in Sequential Circuits. Journal of Electronic Testing, Springer Verlag, 1999, 14 (1/2), pp.95-102. 〈lirmm-00345794〉

Communication dans un congrès198 documents

  • Arnaud Virazel, Alberto Bosio, Patrick Girard, Mario Barbareschi. Approximate computing: Design & test for integrated circuits. LATS: Latin American Test Symposium, Mar 2017, Bogota, Colombia. IEEE, 18th IEEE Latin American Test Symposium, 2017, 〈http://tima.univ-grenoble-alpes.fr/conferences/lats/2017/〉. 〈10.1109/LATW.2017.7906737〉. 〈lirmm-01718600〉
  • Arnaud Virazel, Tien Phu Ho, Alberto Bosio. An Advanced Diagnosis Flow for SRAMs. ISTFA: International Symposium for Testing and Failure Analysis, Nov 2017, Pasadena, United States. 43rd International Symposium for Testing and Failure Analysis, 2017, 〈https://www.asminternational.org/web/istfa-2017〉. 〈lirmm-01718596〉
  • Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio. Towards digital circuit approximation by exploiting fault simulation. EWDTS: East-West Design & Test Symposium, Sep 2017, Novi Sad, Serbia. IEEE, 15th IEEE East-West Design & Test Symposium, 2017, 〈10.1109/EWDTS.2017.8110108〉. 〈lirmm-01718583〉
  • Imran Wali, Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, et al.. Towards approximation during test of Integrated Circuits. DDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2017, Dresden, Germany. IEEE, 20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2017, 〈http://ddecs2017.eas.iis.fraunhofer.de〉. 〈10.1109/DDECS.2017.7934574〉. 〈lirmm-01718580〉
  • Ghita Harcha, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi. An effective fault-injection framework for memory reliability enhancement perspectives. DTIS: Design and Technology of Integrated Systems in Nanoscale Era, Apr 2017, Palma de Mallorca, Spain. IEEE, 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2017, 〈10.1109/DTIS.2017.7930172〉. 〈lirmm-01718579〉
  • Alberto Bosio, Patrick Girard, Arnaud Virazel. Test of Low Power Circuits: Issues and Industrial Practices. ICECS: International Conference on Electronics, Circuits and Systems, Dec 2016, Monte Carlo, Monaco. 23rd IEEE International Conference on Electronics, Circuits and Systems, 2016, 〈http://icecs.isep.fr〉. 〈lirmm-01433330〉
  • Deepak Kumar Arora, Darayus Adil Patel, Nc Shahabuddin, Sanjay Kumar, Navin Kumar Dayani, et al.. Analysis of Setup & Hold Margins Inside Silicon for Advanced Technology Nodes. ISQED: International Symposium on Quality Electronic Design, Mar 2016, Santa Clara, CA, United States. 17th International Symposium & Exhibits on Quality Electronic Desgn, pp.295-300, 2016, 〈http://www.isqed.org/English/Archives/2016/index.html〉. 〈10.1109/ISQED.2016.7479217〉. 〈lirmm-01433314〉
  • Alberto Bosio, Philippe Debaud, Patrick Girard, Stéphane Guilhot, Miroslav Valka, et al.. Auto-adaptive ultra-low power IC. DTIS: Design and Technology of Integrated Systems in Nanoscale Era, Apr 2016, Istanbaul, Turkey. IEEE, 11th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2016, 〈http://www.dtis2016.teiath.gr〉. 〈10.1109/DTIS.2016.7483886〉. 〈lirmm-01457361〉
  • Aymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi, et al.. An effective approach for functional test programs compaction. DDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2016, Kosice, Slovakia. IEEE, 19th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2016, 〈http://ddecs2016.fiit.stuba.sk/DDECS_2016/〉. 〈10.1109/DDECS.2016.7482466〉. 〈lirmm-01457396〉
  • Aymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi, et al.. Improving the Functional Test Delay Fault Coverage: A Microprocessor Case Study. ISVLSI: IEEE Computer Society Annual Symposium on VLSI, Jul 2016, Pittsburgh, PA, United States. IEEE, VLSI (ISVLSI), 2016 IEEE Computer Society Annual Symposium on, pp.731-736, 2016, 〈10.1109/ISVLSI.2016.42 〉. 〈lirmm-01446917〉
  • Alejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard, Cyril Chevalier. A hybrid power modeling approach to enhance high-level power models. DDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2016, Kosice, Slovakia. IEEE, 19th International Symposium on Design and Diagnostics of Electronic Circuits Systems, 2016, 〈http://ddecs2016.fiit.stuba.sk/DDECS_2016/〉. 〈10.1109/DDECS.2016.7482453〉. 〈lirmm-01446854〉
  • Alejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard, Cyril Chevalier. A Hybrid Power Estimation Technique to improve IP power models quality. VLSI-SoC: Very Large Scale Integration and System-on-Chip, Sep 2016, Tallin, Estonia. 24th IFIP/IEEE International Conference on Very Large Scale Integration, 2016, 〈http://ati.ttu.ee/vlsi-soc2016/〉. 〈10.1109/VLSI-SoC.2016.7753582〉. 〈lirmm-01689544〉
  • Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Leonardo B. Zordan. An effective BIST architecture for power-gating mechanisms in low-power SRAMs. ISQED: International Symposium on Quality Electronic Design, Mar 2016, Santa Clara, CA, United States. IEEE, 17th International Symposium on Quality Electronic Design, pp.185-191, 2016, 〈http://www.isqed.org/English/Archives/2016/〉. 〈10.1109/ISQED.2016.7479198〉. 〈lirmm-01457424〉
  • Imran Wali, Bastien Deveautour, Arnaud Virazel, Alberto Bosio, Patrick Girard, et al.. A Low-Cost Reliability vs. Cost Trade-Off Methodology to Selectively Harden Logic Circuits. ETS: European Test Symposium, May 2016, Amsterdam, Netherlands. 21th IEEE European Test Symposium, 2016, 〈http://www.ets16.nl/〉. 〈10.1109/ETS.2016.7519296〉. 〈hal-01444734〉
  • Imran Wali, Arnaud Virazel, Alberto Bosio, Patrick Girard. An Experimental Comparative Study of Fault-Tolerant Architectures. VALID: Advances in System Testing and Validation Lifecycle, Nov 2015, Barcelone, Spain. IARIA XPS Press, 7th International Conference on Advances in System Testing and Validation Lifecycle, pp.1-6, 2015, 〈http://www.iaria.org/conferences2015/VALID15.html〉. 〈lirmm-01354754〉
  • Alejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard, Cyril Chevalier. An efficient hybrid power modeling approach for accurate gate-level power estimation. ICM: International Conference on Microelectronics, Dec 2015, Casablanca, Morocco. 27th International Conference on Microelectronics, pp.17-20, 2015, 〈10.1109/ICM.2015.7437976〉. 〈lirmm-01354745〉
  • Aymen Touati, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, et al.. Exploring the impact of functional test programs re-used for power-aware testing. DATE: Design, Automation and Test in Europe, Mar 2015, Grenoble, France. pp.1277-1280, 2015. 〈lirmm-01272937〉
  • Imran Wali, Arnaud Virazel, Alberto Bosio, Patrick Girard, Matteo Sonza Reorda. Design space exploration and optimization of a Hybrid Fault-Tolerant Architecture. IOLTS: International On-Line Testing Symposium, Jul 2015, Halkidiki, Greece. On-Line Testing Symposium (IOLTS), 2015 IEEE 21st International, pp.89-94, 2015, 〈http://tima.imag.fr/conferences/iolts/iolts15/〉. 〈10.1109/IOLTS.2015.7229838〉. 〈lirmm-01272735〉
  • Miroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, et al.. Design-for-Diagnosis Architecture for Power Switches. DDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2015, Belgrade, Serbia. pp.43-48, 2015, 〈10.1109/DDECS.2015.18〉. 〈lirmm-01272684〉
  • Anu Asokan, Alberto Bosio, Arnaud Virazel, Luigi Dilillo, Patrick Girard, et al.. An ATPG Flow to Generate Crosstalk-Aware Path Delay Pattern. ISVLSI: IEEE Computer Society Annual Symposium on VLSI, Jul 2015, Montpellier, France. pp.515-520, 2015, 〈10.1109/ISVLSI.2015.99〉. 〈lirmm-01272933〉
  • Aymen Touati, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, et al.. Scan-chain intra-cell defects grading. DTIS: Design and Technology of Integrated Systems in Nanoscale Era, Apr 2015, Naples, Italy. Design Technology of Integrated Systems in Nanoscale Era (DTIS), 2015 10th International Conference on, pp.1-6, 2015, 〈10.1109/DTIS.2015.7127349〉. 〈lirmm-01272696〉
  • Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Paolo Bernardi, et al.. An effective ATPG flow for Gate Delay Faults. DTIS: Design and Technology of Integrated Systems in Nanoscale Era, Apr 2015, Naples, Italy. Design Technology of Integrated Systems in Nanoscale Era (DTIS), 2015 10th International Conference on, pp.1-6, 2015, 〈http://www.dtis2015.teiath.gr/〉. 〈10.1109/DTIS.2015.7127350〉. 〈lirmm-01272719〉
  • Imran Wali, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard. An effective hybrid fault-tolerant architecture for pipelined cores. ETS: European Test Symposium, May 2015, Cluj-Napoca, Romania. 20th IEEE European Test Symposium, pp.1-6, 2015, 〈10.1109/ETS.2015.7138733〉. 〈lirmm-01272730〉
  • Sylvain Clerc, Fady Abouzeid, Darayus Adil Patel, Jean-Marc Daveau, Cyril Bottoni, et al.. Design and performance parameters of an ultra-low voltage, single supply 32bit processor implemented in 28nm FDSOI technology. ISQED: International Symposium on Quality Electronic Design, Apr 2015, Santa Clara, United States. Quality Electronic Design (ISQED), 2015 16th International Symposium on, pp.366-370, 2015, 〈10.1109/ISQED.2015.7085453〉. 〈lirmm-01272913〉
  • Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, et al.. Real-Time Testing of 90nm COTS SRAMs at Concordia Station in Antarctica. NSREC: Nuclear and Space Radiation Effects Conference, Jul 2014, Paris, France. IEEE Nuclear & Space Radiation Effects Conference (NSREC 2014), 2014, 〈http://ieee-npss.org/wp-content/uploads/2014/03/2014-NSREC.pdf〉. 〈lirmm-01237709〉
  • Yuanqing Cheng, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, et al.. Power supply noise-aware workload assignments for homogeneous 3D MPSoCs with thermal consideration. ASP-DAC: Asia and South Pacific Design Automation Conference, Jan 2014, Singapore, Singapore. 19th Asia and South Pacific Design Automation Conference, 2014, 〈10.1109/ASPDAC.2014.6742948〉. 〈lirmm-01800279〉
  • Aymen Touati, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, et al.. A Comprehensive Evaluation of Functional Programs for Power-Aware Test. NATW: North Atlantic Test Workshop, May 2014, Johnson City, NY, United States. IEEE, Test Workshop (NATW), 2014 IEEE 23rd North Atlantic, pp.69-72, 2014, 〈10.1109/NATW.2014.23〉. 〈lirmm-01248597〉
  • Carolina Metzler, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, et al.. Timing-aware ATPG for critical paths with multiple TSVs. DDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2014, Warsaw, Poland. IEEE, Design and Diagnostics of Electronic Circuits & Systems, 17th International Symposium on, pp.116-121, 2014, 〈10.1109/DDECS.2014.6868774〉. 〈lirmm-01248600〉
  • Imran Wali, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, et al.. Protecting combinational logic in pipelined microprocessor cores against transient and permanent faults. DDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2014, Warsaw, Poland. Design and Diagnostics of Electronic Circuits Systems, 17th International Symposium on, pp.223-225, 2014, 〈10.1109/DDECS.2014.6868794〉. 〈lirmm-01248598〉
  • Anu Asokan, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, et al.. Path delay test in the presence of multi-aggressor crosstalk, power supply noise and ground bounce. DDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2014, Warsaw, Poland. IEEE, Design and Diagnostics of Electronic Circuits & Systems, 17th International Symposium on, pp.207-212, 2014, 〈10.1109/DDECS.2014.6868791〉. 〈lirmm-01248599〉
  • Miroslav Valka, Alberto Bosio, Luigi Dilillo, Aida Todri-Sanial, Arnaud Virazel, et al.. Test and diagnosis of power switches. DDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2014, Warsaw, Poland. Design and Diagnostics of Electronic Circuits Systems, 17th International Symposium on, pp.213-218, 2014, 〈10.1109/DDECS.2014.6868792〉. 〈lirmm-01248590〉
  • Anu Asokan, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, et al.. A Delay Probability Metric for Input Pattern Ranking Under Process Variation and Supply Noise. ISVLSI: IEEE Computer Society Annual Symposium on VLSI, Jul 2014, Tampa, FL, United States. VLSI (ISVLSI), 2014 IEEE Computer Society Annual Symposium on, pp.226-231, 2014, 〈10.1109/ISVLSI.2014.42〉. 〈lirmm-01248592〉
  • Carolina Metzler, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, et al.. TSV aware timing analysis and diagnosis in paths with multiple TSVs. ISVLSI: IEEE Computer Society Annual Symposium on VLSI, Apr 2014, Napa, CA, United States. VLSI Test Symposium (VTS), 2014 IEEE 32nd, pp.1-6, 2014, 〈10.1109/VTS.2014.6818772〉. 〈lirmm-01248594〉
  • Yuanqing Cheng, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, et al.. Power supply noise-aware workload assignments for homogeneous 3D MPSoCs with thermal consideration. ASP-DAC: Asia and South Pacific Design Automation Conference, Jan 2014, Singapore, Singapore. pp.544-549, 2014, Design Automation Conference (ASP-DAC), 2014 19th Asia and South Pacific. 〈10.1109/ASPDAC.2014.6742948〉. 〈lirmm-01248596〉
  • Miroslav Valka, Alberto Bosio, Luigi Dilillo, Aida Todri-Sanial, Arnaud Virazel, et al.. iBoX — Jitter based Power Supply Noise sensor. ETS: European Test Symposium, May 2014, Paderborn, United States. Test Symposium (ETS), 2014 19th IEEE European, pp.1-2, 2014, 〈10.1109/ETS.2014.6847830〉. 〈lirmm-01248601〉
  • Zhenzhou Sun, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, et al.. On the Generation of Diagnostic Test Set for Intra-cell Defects. ATS: Asian Test Symposium, Nov 2014, Hangzhou, China. Test Symposium (ATS), 2014 IEEE 23rd Asian, pp.312-317, 2014, 〈10.1109/ATS.2014.57〉. 〈lirmm-01272539〉
  • Georgios Tsiligiannis, Luigi Dilillo, Viyas Gupta, Alberto Bosio, Patrick Girard, et al.. Efficient Dynamic Test Methods for COTS SRAMs Under Heavy Ion Irradiation. NSREC: Nuclear and Space Radiation Effects Conference, Jul 2014, Paris, France. IEEE Nuclear & Space Radiation Effects Conference (NSREC 2014), 2014. 〈lirmm-01237660〉
  • Leonardo Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, et al.. On the Reuse of Read and Write Assist Circuits to Improve Test Efficiency in Low-Power SRAMs. ITC: International Test conference, Sep 2013, Anaheim, CA, United States. pp.1-10, 2013, 〈http://www.itctestweek.org/〉. 〈10.1109/TEST.2013.6651927〉. 〈lirmm-00818977〉
  • Georgios Tsiligiannis, Ioana Vatajelu, Luigi Dilillo, Alberto Bosio, Patrick Girard, et al.. SRAM Soft Error Rate Evaluation Under Atmospheric Neutron Radiation and PVT variations. IOLTS: International On-Line Testing Symposium, Jul 2013, Chania, Crete, Greece. On-Line Testing Symposium (IOLTS), 2013 IEEE 19th International, pp.145-150, 2013, 〈http://tima.imag.fr/conferences/iolts/iolts13/〉. 〈10.1109/IOLTS.2013.6604066〉. 〈lirmm-00818955〉
  • Ioana Vatajelu, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, et al.. Analyzing Resistive-Open Defects in SRAM Core-Cell under the Effect of Process Variability. ETS: European Test Symposium, May 2013, Avignon, France. Test Symposium (ETS), 2013 18th IEEE European, pp.1-6, 2013, 〈10.1109/ETS.2013.6569373〉. 〈lirmm-00805360〉
  • Carolina Metzler, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, et al.. Computing Detection Probability of Delay Defects in Signal Line TSVs. ETS: European Test Symposium, May 2013, Avignon, France. Test Symposium (ETS), 2013 18th IEEE, 2013, 〈10.1109/ETS.2013.6569349〉. 〈lirmm-00839044〉
  • Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, et al.. SEU Monitoring in Mixed-Field Radiation Environments of Particle Accelerators. RADECS: Radiation and Its Effects on Components and Systems, Sep 2013, Oxford, United Kingdom. 14th European Conference on Radiation and Its Effects on Components and Systems, pp.1-4, 2013, 〈10.1109/RADECS.2013.6937419〉. 〈lirmm-00839085〉
  • Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, et al.. Characterization of an SRAM Based Particle Detector For Mixed-Field Radiation Environments. IWASI: International Workshop on Advances in Sensors and Interfaces, Jun 2013, Bari, Italy. 5th IEEE International Workshop on Advances in Sensors and Interfaces, pp.75-80, 2013, 〈10.1109/IWASI.2013.6576070〉. 〈lirmm-00839046〉
  • Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, et al.. Worst-Case Power Supply Noise and Temperature Distribution Analysis for 3D PDNs with Multiple Clock Domains. NEWCAS: New Circuits and Systems, Jun 2013, Paris, France. 11th International IEEE Conference on New Circuits and Systems, 2013, 〈http://newcas2013.org〉. 〈10.1109/NEWCAS.2013.6573628〉. 〈lirmm-00839042〉
  • Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel. Fast and Accurate Electro-Thermal Analysis of Three-Dimensional Power Delivery Networks. EuroSimE: Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems, Apr 2013, Wroclaw, Poland. Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE), 2013 14th International Conference on, pp.1-4, 2013, 〈10.1109/EuroSimE.2013.6529956〉. 〈lirmm-00839043〉
  • Yuanqing Cheng, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, et al.. Mitigate TSV Electromigration for 3D ICs - From the Architecture Perspective. International Symposium on VLSI, Natale, Brazil. pp.6, 2013. 〈lirmm-00839052〉
  • Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, et al.. Multiple-Cell-Upsets on a commercial 90nm SRAM in Dynamic Mode. RADECS: Radiation and Its Effects on Components and Systems, Sep 2013, Oxford, United Kingdom. 14th European Conference on Radiation and Its Effects on Components and Systems, pp.1-4, 2013, 〈10.1109/RADECS.2013.6937429〉. 〈lirmm-00839062〉
  • Leonardo Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, et al.. Test Solution for Data Retention Faults in Low-Power SRAMs. EDA Association. DATE: Design, Automation and Test in Europe, Mar 2013, Grenoble, France. Design, Automation & Test in Europe Conference & Exhibition, pp.442-447, 2013, 〈http://www.date-conference.com/〉. 〈10.7873/DATE.2013.099〉. 〈lirmm-00805140〉
  • Ioana Vatajelu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Aida Todri-Sanial, et al.. Adaptive Source Bias for Improved Resistive-Open Defect Coverage during SRAM Testing. ATS: Asian Test Symposium, Nov 2013, Jiaosi Township, Taiwan. pp.109-114, 2013, 〈10.1109/ATS.2013.30〉. 〈lirmm-01248609〉
  • Yuanqing Cheng, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, et al.. A novel method to mitigate TSV electromigration for 3D ICs. ISVLSI: IEEE Computer Society Annual Symposium on VLSI, Aug 2013, Natal, Brazil. pp.121-126, 2013, 〈10.1109/ISVLSI.2013.6654633〉. 〈lirmm-01248617〉
  • Ioana Vatajelu, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, et al.. Analyzing the effect of concurrent variability in the core cells and sense amplifiers on SRAM read access failures. DTIS: Design and Technology of Integrated Systems in Nanoscale Era, Mar 2013, Abu Dhabi, United Arab Emirates. 8th International Conference on Design Technology of Integrated Systems in Nanoscale Era, pp.39-44, 2013, 〈10.1109/DTIS.2013.6527775〉. 〈lirmm-01248603〉
  • Zhenzhou Sun, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, et al.. Improving Defect Localization Accuracy by means of Effect-Cause Intra-Cell Diagnosis at Transistor Level. SDD: Silicon Debug and Diagnosis, Sep 2013, Anaheim, CA, United States. 8th IEEE International Workshop on Silicon Debug and Diagnosis, 2013, 〈http://sdd.tttc-events.org/13/〉. 〈lirmm-00806872〉
  • Zhenzhou Sun, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, et al.. Effect-Cause Intra-Cell Diagnosis at Transistor Level. ISQED: International Symposium on Quality Electronic Design, Mar 2013, Santa Clara, CA, United States. 14th International Symposium on Quality Electronic Design, pp.460-467, 2013, 〈http://www.isqed.org/〉. 〈10.1109/ISQED.2013.6523652〉. 〈lirmm-00817224〉
  • Ioana Vatajelu, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, et al.. Analyzing resistive-open defects in SRAM core-cell under the effect of process variability. ETS: European Test Symposium, May 2013, Avignon, France. 18th IEEE European Test Symposium, 2013, 〈10.1109/ETS.2013.6569373〉. 〈lirmm-01921630〉
  • João Azevedo, Arnaud Virazel, Yuanqing Cheng, Alberto Bosio, Luigi Dilillo, et al.. Performance Characterization of TAS-MRAM Architectures in Presence of Capacitive Defects. VALID: Advances in System Testing and Validation Lifecycle, Oct 2013, Venice, Italy. 5th International Conference on Advances in System Testing and Validation Lifecycle, pp.39-44, 2013, 〈https://www.iaria.org/conferences2013/VALID13.html〉. 〈lirmm-01433308〉
  • Leonardo Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, et al.. A Built-in Scheme for Testing and Repairing Voltage Regulators of Low-Power SRAMs. VTS: VLSI Test Symposium, Apr 2013, Berkeley, CA, United States. IEEE 31st VLSI Test Symposium, pp.1-6, 2013, 〈http://www.tttc-vts.org/public_html/new/2013/index.php〉. 〈10.1109/VTS.2013.6548894〉. 〈lirmm-00805366〉
  • Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, et al.. Evaluating An SEU Monitor For Mixed-Field Radiation Environments. iWoRID: International Workshop on Radiation Imaging Detectors, Jun 2013, Paris, France. 15th International Workshops on Radiation Imaging Detectors, 2013, 〈http://www.synchrotron-soleil.fr/Workshops/2013/IWORID2013〉. 〈lirmm-01238433〉
  • Ioana Vatajelu, Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, et al.. On the correlation between Static Noise Margin and Soft Error Rate evaluated for a 40nm SRAM cell. DFT: Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Oct 2013, New York, United States. Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2013 IEEE International Symposium on, pp.143-148, 2013, 〈http://www.dfts.org/dft13/〉. 〈10.1109/DFT.2013.6653597〉. 〈lirmm-01238413〉
  • Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, et al.. Temperature Impact on the Neutron SER of a Commercial 90nm SRAM. NSREC: Nuclear and Space Radiation Effects Conference, Jul 2013, San Francisco, Ca, United States. IEEE, pp.1-4, 2013, 〈http://www.nsrec.com/〉. 〈lirmm-00805291〉
  • Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Aida Todri-Sanial, et al.. SRAM testing under Neutron Radiation for the evaluation of different algorithms stress. 15ème Journées Nationales du Réseau Doctoral en Microélectronique, Jun 2012, Marseille, France. 2012, 〈http://jnrdm2012.im2np.fr/〉. 〈lirmm-00807054〉
  • Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Arnaud Virazel. Why and How Controlling Power Consumption During Test: A Survey. ATS: Asian Test Symposium, Nov 2012, Niigata, Japan. Test Symposium (ATS), 2012 IEEE 21st Asian, pp. 221-226, 2012, 〈http://aries3a.cse.kyutech.ac.jp/~ats12/〉. 〈10.1109/ATS.2012.30〉. 〈lirmm-00818984〉
  • João Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, et al.. Impact of Resistive-Open Defects on the Heat Current of TAS-MRAM Architectures. DATE: Design, Automation and Test in Europe, Mar 2012, Dresden, Germany. Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012, pp.532-537, 2012, 〈10.1109/DATE.2012.6176526〉. 〈lirmm-00689024〉
  • Ahn Duc Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, et al.. Robustness Improvement of Digital Circuits A New Hybrid Fault Tolerant Architecture. JNRDM'11: Journées Nationales du Réseau Doctoral de Microélectronique, Paris, France. 2011. 〈lirmm-00679509〉
  • Ahn Duc Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, et al.. A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits. GDR SOC-SIP'11 : Colloque GDR SoC-SiP, Lyon, France. 2011. 〈lirmm-00679513〉
  • Leonardo Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, et al.. Optimized March Test Flow for Detecting Memory Faults in SRAM Devices Under Bit Line Coupling. GDR SOC-SIP'11 : Colloque GDR SoC-SiP, Lyon, France. 2011. 〈lirmm-00679522〉
  • João Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, et al.. Test and Reliability of Magnetic Random Access Memories. GDR SOC-SIP'11: Colloque GDR SoC-SiP, Lyon, France. 2011. 〈lirmm-00679516〉
  • Arnaud Virazel. Impact of Technology Scaling on Defects and Parameter Deviations in Embedded SRAMs. NVM'11: Leading-Edge Embedded NVM Workshop, Gardane, France. 2011, 〈http://www.arcsis.org/1690.0.html?&L=1〉. 〈lirmm-00679494〉
  • Leonardo Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, et al.. Defect Analysis in Power Mode Control Logic of Low-Power SRAMs. ETS: European Test symposium, May 2012, Annecy, France. 17th IEEE European Test Symposium, 2012, 〈http://ets2012.imag.fr/〉. 〈10.1109/ETS.2012.6233033〉. 〈lirmm-00805374〉
  • Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Aida Todri-Sanial, et al.. Evaluation of Test Algorithms Stress Effect on SRAMs under Neutron Radiation. IEEE. IOLTS'2012: International On-Line VLSI Test symposium, Jun 2012, Sitges, Spain. pp.212-222, 2012, 〈http://tima.imag.fr/conferences/iolts/iolts12/〉. 〈10.1109/IOLTS.2012.6313853〉. 〈lirmm-00805373〉
  • João Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, et al.. Impact of Resistive-Bridge Defects in TAS-MRAM Architectures. ATS: Asian Test Symposium, Nov 2012, Niigata, Japan. 21st IEEE Asian Test Symposium, pp.125-130, 2012, 〈10.1109/ATS.2012.37〉. 〈lirmm-00806809〉
  • Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, et al.. Radiation Induced Effects on Electronic Systems and ICs. SETS: South European Test Seminar, Mar 2012, Sauze d'Oulx, Italy. South European Test Seminar, 2012, 〈http://www.cad.polito.it/SETS12/〉. 〈lirmm-00807055〉
  • Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Aida Todri-Sanial, et al.. Dynamic Mode Testing of SRAMS under Neutron Radiation. Sixième colloque du GDR SOC-SIP du CNRS, Jun 2012, Paris, France. 2012, 〈http://www2.lirmm.fr/~w3mic/SOCSIP/index.php/colloque/colloque-2012〉. 〈lirmm-00807053〉
  • Leonardo Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, et al.. Low-power SRAMs Power Mode Control Logic: Failure Analysis and Test Solutions. ITC'2012: International Test Conference, Nov 2012, Anaheim, CA, United States. IEEE, pp.1-10, 2012, 〈http://www.itctestweek.org/〉. 〈10.1109/TEST.2012.6401578〉. 〈lirmm-00805143〉
  • Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel. Advanced Test Methods for SRAMs. VTS: VLSI Test Symposium, Apr 2012, Hyatt Maui, HI, United States. IEEE, 30th IEEE VLSI Test Symposium (VTS), pp.300-301, 2012, 〈http://www.tttc-vts.org/public_html/new/2012/〉. 〈10.1109/VTS.2012.6231070〉. 〈lirmm-00805049〉
  • Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Aida Todri-Sanial, et al.. A Novel Framework for Evaluating the SRAM Core-Cell Sensitivity to Neutrons. RADECS: European Conference on Radiation and Its Effects on Components and Systems, Sep 2012, Biarritz, France. pp.1-4, 2012, 〈http://www.ims-bordeaux.fr/RADECS2012/pages/pageDynamiqueSITEExt.php?guidPage=home_page〉. 〈lirmm-00805163〉
  • Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Aida Todri-Sanial, et al.. Dynamic Mode Test of a Commercial 4Mb Toggle MRAM under Neutron Radiation. RADECS: European Conference on Radiation and Its Effects on Components and Systems, Sep 2012, Biarritz, France. pp.1-4, 2012, 〈http://www.ims-bordeaux.fr/RADECS2012/pages/pageDynamiqueSITEExt.php?guidPage=home_page〉. 〈lirmm-00805165〉
  • Ahn Duc Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, et al.. A Pseudo-Dynamic Comparator for Error Detection in Fault Tolerant Architectures. VTS: VLSI Test Symposium, Apr 2012, Hawaii, United States. VLSI Test Symposium (VTS), 2012 IEEE 30th, pp.50-55, 2012, 〈10.1109/VTS.2012.6231079〉. 〈lirmm-00806778〉
  • João Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, et al.. Impacts of Resistive-Open Defects in the Word-Line Selection of TAS-MRAMs. Colloque GDR SoC-SiP, 2012, Paris, France. 2012. 〈lirmm-00806842〉
  • Zhenzhou Sun, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, et al.. Defect Localization Through an Effect-Cause based Intra-Cell Diagnosis. Colloque GDR SoC-SiP, 2012, Paris, France. 2012. 〈lirmm-00806841〉
  • Miroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, et al.. Adaptive Voltage Scaling via Effective On-Chip Timing Uncertainty Measurements. Colloque GDR SoC-SiP, 2012, Paris, France. 2012. 〈lirmm-00806859〉
  • Carolina Metzler, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, et al.. Through-Silicon-Via Resistive-Open Defect Analysis. ETS: European Test Symposium, May 2012, Annecy, France. Test Symposium (ETS), 2012 17th IEEE European, 2012, 〈10.1109/ETS.2012.6233037〉. 〈lirmm-00806848〉
  • Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel. Electro-Thermal Analysis of 3D Power Delivery Networks. DAC: Design Automation Conference, 2012, San Francisco, United States. 49th Design Automation Conference Work-in-Progress (WIP) Track, 2012. 〈lirmm-00806836〉
  • Carolina Metzler, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, et al.. Resistive-Open Defect Analysis for Through-Silicon-Vias. DCIS: Design of Circuits and Integrated Systems, 2012, Avignon, France. XXVII Conference on Design of Circuits and Integrated Systems, 2012. 〈lirmm-00806803〉
  • Zhenzhou Sun, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, et al.. Fault Localization Improvement through an Intra-Cell Diagnosis Approach. 38th International Symposium for Testing and Failure Analysis, Nov 2012, United States. pp.509-519, 2012. 〈lirmm-00806863〉
  • João Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, et al.. Resistive-Open Defects Affecting Bit-Line Selection in TAS-MRAM Architectures. JNRDM: Journées Nationales du Réseau Doctoral en Microélectronique, 2012, Paris, France. 2012. 〈lirmm-00806827〉
  • Miroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, et al.. Power Supply Noise Sensor Based on Timing Uncertainty Measurements. ATS: Asian Test Symposium, Nov 2012, Niigata, Japan. 21st IEEE Asian Test Symposium, pp.161-166, 2012, 〈10.1109/ATS.2012.46〉. 〈lirmm-00806890〉
  • João Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, et al.. Analysis of Resistive-Open Defects in TAS-MRAM Array. ITC: International Test Conference, Sep 2011, Anaheim, CA, United States. 2011. 〈lirmm-00679524〉
  • Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, et al.. On Using Address Scrambling for Defect Tolerance in SRAMs. International test Conference, Sep 2011, Anaheim, CA, United States. IEEE, pp.1-8, 2012, 〈http://www.itctestweek.org/〉. 〈10.1109/TEST.2011.6139149〉. 〈lirmm-00805334〉
  • Luigi Dilillo, Alberto Bosio, Miroslav Valka, Patrick Girard, Serge Pravossoudovitch, et al.. Error Resilient Infrastructure for Data Transfer in a Distributed Neutron Detector. DFT'11: International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Vancouver, Canada. IEEE, pp.N/A, 2011. 〈lirmm-00651226〉
  • Kohei Miyase, Yuta Uchinodan, Kazunari Enokimoto, Yuta Yamato, Xiaoqing Wen, et al.. Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-Filling. ATS: Asian Test Symposium, 2011, New Delhi, India. 20th IEEE Asian Test Symposium, pp.21-23, 2011. 〈lirmm-00651247〉
  • Ahn Duc Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, et al.. A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits Parity Prediction Synthesis for Nano-Electronic Gate Designs. ATS: Asian Test Symposium, Nov 2011, New Delhi, India. 20th IEEE Asian Test Symposium, pp.136-141, 2011. 〈lirmm-00651238〉
  • Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, et al.. Mapping Test Power to Functional Power through Smart X-Filling for LOS Scheme. LPonTR'11: IEEE International Workshop on the Impact of Low Power on Test and Reliability, Trondheim, Norway. 2011. 〈lirmm-00651905〉
  • Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel. Robust Structure for Data Collection and Transfer in a Distributed SRAM Based Neutron Test Bench. Workshop on Dependability Issues in Deep-Submicron Technologies, Trondheim, Norway. 2011. 〈lirmm-00651796〉
  • Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, et al.. Simultaneous Power and Thermal Integrity Analysis for 3D Integrated Systems. LPonTR'11: IEEE International Workshop on the Impact of Low Power on Test and Reliability, Trondheim, Norway. 2011. 〈lirmm-00651802〉
  • Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, et al.. A DfT Solution for Oxide Thickness Varitions in ATMEL eFlash Technology. DTIS: Design and Technology of Integrated Systems in Nanoscale Era, 2011, Athènes, Greece. 2011. 〈lirmm-00647750〉
  • Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, et al.. Power Reduction Through X-filling of Transition Fault Test Vectors for LOS Testing. DTIS: Design and Technology of Integrated Systems in Nanoscale Era, 2011, Athènes, Greece. Design and Technology of Integrated Systems in Nanoscale Era, 2011, 〈10.1109/DTIS.2011.5941434〉. 〈lirmm-00647760〉
  • Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, et al.. Power Supply Noise and Ground Bounce Aware Pattern Generation for Delay Testing. NEWCAS: International New Circuits and Systems Conference, Jun 2011, Bordeaux, France. New Circuits and Systems Conference (NEWCAS), 2011 IEEE 9th International, pp.73-76, 2011, 〈10.1109/NEWCAS.2011.5981222〉. 〈lirmm-00647815〉
  • Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, et al.. On Using Address Scrambling to Implement Defect Tolerance in SRAMs. ITC'2011: International Test Conference, Sep 2011, Anaheim, CA, United States. IEEE, pp.N/A, 2011. 〈lirmm-00647773〉
  • Miroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, et al.. A Functional Power Evaluation Flow for Defining Test Power Limits During At-Speed Delay Testing. ETS: European Test Symposium, May 2011, Trondheim, Norway. 16th IEEE European Test Symposium, pp.153-158, 2011. 〈lirmm-00647822〉
  • Leonardo Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, et al.. Failure Analysis and Test Solutions for Low-Power SRAMs. ATS: Asian Test Symposium, Nov 2011, New Delhi, India. 20th IEEE Asian Test Symposium, pp.459-460, 2011, 〈http://www.ecs.umass.edu/ece/ats11/〉. 〈10.1109/ATS.2011.97〉. 〈lirmm-00805123〉
  • Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, et al.. Test Relaxation and X-filling to Reduce Peak Power During At-Speed LOS Testing. GDR SOC-SIP'10 : Colloque GDR SoC-SiP, Cergy, France. 2010. 〈lirmm-00553989〉
  • Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, et al.. Analyse et modélisation des défauts résistifs affectant les mémoires Flash. GDR SOC-SIP'10 : Colloque GDR SoC-SiP, Cergy, France. 2010. 〈lirmm-00553947〉
  • Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, et al.. Analysis and Fault Modeling of Actual Resistive Defects in Flash Memories. JNRDM'10 : Journées Nationales du Réseau Doctoral de Microélectronique, Montpellier, France. 2010. 〈lirmm-00553935〉
  • Ahn Duc Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, et al.. Tolérance aux fautes et rendement de fabrication. GDR SOC-SIP'10 : Colloque GDR SoC-SiP, Cergy, France. 2010. 〈lirmm-00553995〉
  • Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, et al.. Variability Analysis of an SRAM Test Chip. ETS: European Test Symposium, May 2011, Trondheim, Norway. 16th IEEE European Test Symposium, 2011. 〈lirmm-00651791〉
  • Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Arnaud Virazel, et al.. Power-Aware Test Pattern Generation for At-Speed LOS Testing. ATS: Asian Test Symposium, Nov 2011, New Delhi, India. Test Symposium (ATS), 2011 20th Asian, pp.506-510, 2011, 〈http://www.ecs.umass.edu/ece/ats11/files/ats2011_cfp_rev1.pdf〉. 〈lirmm-00651917〉
  • Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, et al.. Impact of Resistive-Bridging Defects in SRAM Core-Cell. DELTA'10: International Symposium on Electronic Design, Test & Applications, Ho Chi Minh, Vietnam. pp.265-270, 2010. 〈lirmm-00553592〉
  • Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, et al.. Detecting NBTI Induced Failures in SRAM Core-Cells. VTS'10: VLSI Test Symposium, Santa Cruz, CA, United States. IEEE Computer Society Press, pp.75-80, 2010. 〈lirmm-00553612〉
  • Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, et al.. A Study of Path Delay Variations in the Presence of Uncorrelated Power and Ground Supply Noise. DDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2011, Cottbus, Germany. Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2011 IEEE 14th International Symposium on, pp.189-194, 2011, 〈10.1109/DDECS.2011.5783078〉. 〈lirmm-00592000〉
  • Leonardo Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, et al.. Optimized March Test Flow for Detecting Memory Faults in SRAM Devices Under Bit Line Coupling. DDECS'11: 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits ans Systems, Netherlands. pp.353-358, 2011. 〈lirmm-00592182〉
  • Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, et al.. On Using a SPICE-Like TSTAC eFlash Model for Design and Test. DDECS'11: 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits ans Systems, Netherlands. pp.359-370, 2011. 〈lirmm-00592203〉
  • Paolo Rech, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, et al.. A Memory Fault Simulator for Radiation-Induced Effects in SRAMs. ATS: Asian Test Symposium, 2010, Shanghai, China. 19th IEEE Asian Test Symposium, pp.100-105, 2010. 〈lirmm-00545102〉
  • Youssef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, et al.. A Comprehensive System-on-Chip Logic Diagnosis. ATS: Asian Test Symposium, 2010, Shanghai, China. 19th IEEE Asian Test Symposium, pp.237-242, 2010. 〈lirmm-00545131〉
  • Wu Fangmei, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, et al.. Analysis of Power Consumption and Transition Fault Coverage for LOS and LOC Testing Schemes. DDECS'10: 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Apr 2010, Vienna, Austria. pp.376-381, 2010. 〈lirmm-00475734〉
  • Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, et al.. Setting Test Conditions for Detecting Faults Induced by Random Dopant Fluctuation in SRAM Core-Cells. VARI: Workshop on CMOS Variability, 2010, Montpellier, France. 2010. 〈lirmm-00553626〉
  • Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, et al.. A Statistical Simulation Method for Reliability Analysis of SRAM Core-Cells. DAC: Design Automation Conference, Jun 2010, Anaheim, United States. IEEE Computer Society Press, 47th Design Automation Conference, pp.853-856, 2010, 〈https://dac.com/content/47th-dac〉. 〈lirmm-00553619〉
  • Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, et al.. Power Reduction Through X-filling of Transition Fault Test Vectors for LOS Testing. LPonTR: 
Impact of Low-Power design on Test and Reliability, May 2010, Prague, Czech Republic. 3rd International Workshop on 
Impact of Low-Power design on Test and Reliability, 2010, 〈https://www.staff.ncl.ac.uk/a.bystrov/LPonTR/2010/LPonTR-10-CfP.pdf〉. 〈lirmm-00553930〉
  • Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, et al.. Analysis of Resistive-Bridging Defects in SRAM Core-Cells: a Comparative Study from 90nm down to 40nm Technology Nodes. ETS: European Test Symposium, May 2010, Prague, Czech Republic. 15th IEEE European Test Symposium, pp.132-137, 2010. 〈lirmm-00493236〉
  • Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, et al.. A Two-Layer SPICE Model of the ATMEL TSTAC eFlash Memory Technology for Defect Injection and Faulty Behavior Prediction. ETS: European Test Symposium, May 2010, Prague, Czech Republic. 15th IEEE European Test Symposium, pp.81-86, 2010. 〈lirmm-00493204〉
  • Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, et al.. Setting Test Conditions for Improving SRAM Reliability. ETS: European Test Symposium, May 2010, Prague, Czech Republic. 15th IEEE European Test Symposium, pp.257-262, 2010. 〈lirmm-00492741〉
  • Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, et al.. Trade-off Between Power Dissipation and Delay Fault Coverage For LOS and LOC Testing Schemes. Impact of Low-Power Design on Test and Reliability, Spain. 2009. 〈lirmm-00435005〉
  • Julien Vial, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, et al.. Using TMR Architectures for SoC Yield Improvement. VALID'09: The First International Conference on Advances in System Testing and Validation Lifecycle, 2009, Porto, Portugal. pp.155-160, 2009. 〈lirmm-00406967〉
  • Youssef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, et al.. Delay Fault Diagnosis in Sequential Circuits. ATS: Asian Test Symposium, Nov 2009, Taichung, Taiwan. 18th IEEE Asian Test Symposium, pp.355-360, 2009. 〈lirmm-00406968〉
  • Alexandre Ney, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, et al.. A New Design-for-Test Technique for SRAM Core-Cell Stability Faults. DATE: Design, Automation and Test in Europe, Apr 2009, Nice, France. ACM/IEEE, pp.1344-1348, 2009, 〈10.1109/DATE.2009.5090873〉. 〈lirmm-00371374〉
  • Youssef Benabboud, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, et al.. A Fault-Simulation-Based Approach for Logic Diagnosis. DTIS: Design and Technology of Integrated Systems in Nanoscale Era, Apr 2009, Cairo, Egypt. 4th IEEE International Conference on Design and Technology of Integrated Systems in Nanoscale Era, pp.216-221, 2009. 〈lirmm-00371377〉
  • Youssef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, et al.. Comprehensive Bridging Fault Diagnosis based on the SLAT Paradigm. DDECS'09: 12th IEEE Symposium on Design and Diagnostics of Electronic Systems, pp.264-269, 2009. 〈lirmm-00371198〉
  • Youssef Benabboud, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, et al.. A Case Study on Logic Diagnosis for System-on-Chip. ISQED'09: IEEE 10th International Symposium on Quality Electronic Design, Mar 2009, San Jose, CA, USA, pp.253-260, 2009, 〈http://www.isqed.org/〉. 〈lirmm-00370646〉
  • Julien Vial, Arnaud Virazel. Yes, we Can Improve SoC Yield. PRIME'09: Conference on Ph.D. Research in Microelectronics and Electronics, pp.272-275, 2009. 〈lirmm-00433763〉
  • Alexandre Ney, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, et al.. A Signature-based Approach for Diagnosis of Dynamic Faults in SRAMs. DTIS: Design and Technology of Integrated Systems in Nanoscale Era, Mar 2008, Tunis, Tunisia. IEEE, 3rd International Conference on Design and Technology of Integrated Systems in Nanoscale Era, pp.001-006, 2008, 〈10.1109/DTIS.2008.4540243〉. 〈lirmm-00324143〉
  • Luigi Dilillo, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, et al.. Impact of Technology Scaling on Defects and Parameter Deviations in Embedded SRAMs. IEEE Computer Society. VLSI Test Symposium, Apr 2008, San Diego, California, United States. IEEE Conference Publishing Service, pp.336, 2008, 〈http://www.tttc-vts.org/public_html/new/2008/index.php〉. 〈lirmm-00324151〉
  • Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, et al.. Yield Improvement, Fault-Tolerance to the Rescue?. IOLTS'08: 14th IEEE International On-Line Testing Symposium, Jul 2008, Rhodes, Greece, IEEE, pp.165-170, 2008. 〈lirmm-00303400〉
  • Alexandre Ney, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian, et al.. An SRAM Design-for-Diagnosis Solution Based on Write Driver Voltage Sensing. VTS'08: VLSI Test Symposium, May 2008, San Diego, CA, USA, IEEE, pp.89-94, 2008. 〈lirmm-00281558〉
  • R. David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel. Random Adjacent Sequences: An Efficient Solution for Logic BIST. SoC Design Methodologies - International Conference on Very Large Scale Integration of Systems-on-Chips, Montpellier, France, Kluwer Academic Publishers, pp.413-424, 2002. 〈lirmm-00268500〉
  • R. David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel. On Using Efficient Test Sequences for BIST. VTS'02: 20th IEEE VLSI Test Symposium, Monterey, CA, USA, pp.145-150, 2002. 〈lirmm-00268499〉
  • Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, et al.. Using TMR Architectures for Yield Improvement. DFT'08: 23rd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Oct 2008, pp.007-015, 2008, 〈www.dfts.org〉. 〈lirmm-00326901〉
  • Alexandre Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, et al.. A Design-for-Diagnosis Technique for SRAM Write Drivers. DATE: Design, Automation and Test in Europe, 2008, Munich, Germany. EDAA, pp.1480-1485, 2008. 〈lirmm-00341796〉
  • Alexandre Ney, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, et al.. A History-Based Diagnosis Technique for Static and Dynamic Faults in SRAMs. ITC'2008: International Test Conference, Oct 2008, Santa Clara, CA, United States. IEEE, pp.1-10, 2008, 〈10.1109/TEST.2008.4700555〉. 〈lirmm-00341798〉
  • Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, et al.. Améliorer le rendement grâce aux structures tolérantes aux fautes. Journées des Doctorants de l'Ecole Doctorale I2S, France. 2008. 〈lirmm-00341806〉
  • Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, et al.. Tolérer Plus pour Fabriquer Plus. Colloque GDR SoC-SiP, France. 2008. 〈lirmm-00341812〉
  • Julien Vial, Christian Landrault, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, et al.. Utilisation de structures tolérantes aux fautes pour augmenter le rendement. Journées Nationales du Réseau Doctoral de Microélectronique, France. 2008. 〈lirmm-00341811〉
  • Alexandre Ney, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, et al.. A History-Based Technique for Faults Diagnosis in SRAMs. Colloque GDR SoC-SiP, France. 2008. 〈lirmm-00341821〉
  • Patrick Girard, Christian Landrault, Véronique Moreda, Serge Pravossoudovitch, Arnaud Virazel. A New Scan-BIST Structures to Test delay Faults in Sequential Circuits. ETW'98: IEEE European Test Workshop, pp.44-48, 1998. 〈lirmm-00345797〉
  • Arnaud Virazel, René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch. Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences. ETW'00: IEEE European Test Workshop, pp.9-14, 2000. 〈lirmm-00345799〉
  • René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel. On Hardware Generation of Random Single Input Change Test. ETW'01: European Test Workshop, pp.117-123, 2001. 〈lirmm-00345801〉
  • René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel. RSIC Generation: A Solution for Logic BIST. IFIP VLSI-SOC'08: 11th IFIP International Conference on VLSI, pp.111-117, 2001. 〈lirmm-00345802〉
  • Arnaud Virazel, René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch. Test Intégré de Circuits Digitaux : Comparaison de deux types de Séquences de Test. Journées des Doctorants, École Doctorale I2S, France. pp.158-160, 2001. 〈lirmm-00345806〉
  • Arnaud Virazel, Patrick Girard, Christian Landrault, Serge Pravossoudovitch. Analyse des capacités de test de générateurs intégrés produisant des vecteurs adjacents. Colloque CAO de Circuits Intégrés et Systèmes, France. pp.88-91, 1999. 〈lirmm-00345803〉
  • Arnaud Virazel, René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch. Test Intégré de Circuits Digitaux : Etude Comparative de l'Efficacité de deux types de Séquences de Test. Journées Nationales du Réseau Doctoral de Microélectronique, France. pp.86-87, 2000. 〈lirmm-00345804〉
  • Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel. Comparison between Random and Pseudo-Random Generation for BIST of Delay, Stuck-at and Bridging Faults. 6th IEEE International On-Line Testing Workshop, pp.121-161, 2000. 〈lirmm-00345800〉
  • Alberto Bosio, Alexandre Rousset, Patrick Girard, Serge Pravossoudovitch, Christian Landrault, et al.. Improved Diagnosis Resolution without Physical Information. DELTA'08: International Symposium on Electronic Design, Test & Applications, Jan 2008, IEEE, pp.210-215, 2008, 〈http://www.ece.ust.hk/delta2008/〉. 〈lirmm-00260961〉
  • Alexandre Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, et al.. Slow Write Driver Faults in 65nm SRAM Technology: Analysis and March Test Solution. DATE: Design, Automation and Test in Europe, Apr 2007, Nice, France. pp.528-533, 2007, 〈10.1109/DATE.2007.364647〉. 〈lirmm-00187037〉
  • Alexandre Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, et al.. Un-Restored Destructive Write Faults due to Resistive-Open Defects in the Write Driver of SRAMs. VTS'07: 25th IEEE VLSI Test Symposium, May 2007, Berkeley, CA (USA), IEEE, pp.361-366, 2007. 〈lirmm-00155979〉
  • Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Alexandre Rousset, et al.. DERRIC: A Tool for Unified Logic Diagnosis. ETS: European Test Symposium, May 2007, Freiburg, Germany. 12th IEEE European Test Symposium, pp.13-18, 2007, 〈10.1109/ETS.2007.16〉. 〈lirmm-00155993〉
  • Olivier Ginez, Jean-Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, et al.. Retention and Reliability Problems in Embedded Flash Memories: Analysis and Test of Defective 2T-FLOTOX Tunnel Window. VTS'07: 25th IEEE VLSI Test Symposium, May 2007, Berkeley, CA (USA), IEEE, pp.47-52, 2007. 〈lirmm-00151034〉
  • Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, et al.. Fast Bridging Fault Diagnosis using Logic Information. ATS: Asian Test Symposium, Oct 2007, Beijing, China. 16th IEEE Asian Test Symposium, pp.33-38, 2007. 〈lirmm-00179259〉
  • Magali Bastian, V. Gouin, Patrick Girard, Christian Landrault, Alexandre Ney, et al.. Influence of Threshold Voltage Deviations on 90nm SRAM Core-Cell Behavior. ATS: Asian Test Symposium, Oct 2007, Beijing, China. 16th IEEE Asian Test Symposium, pp.501-504, 2007, 〈10.1109/ATS.2007.121〉. 〈lirmm-00179276〉
  • Olivier Ginez, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, et al.. Test des Mémoires Flash Embarquées : Analyse de la perturbation entre cellules FloTOx voisines durant une phase de programmation. Journées Nationales du Réseau Doctoral de Microélectronique, France. 2007. 〈lirmm-00194274〉
  • Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, et al.. Méthode de diagnostic unifiée pour circuits intégrés numériques. Colloque GDR SoC-SiP, France. 2007. 〈lirmm-00194285〉
  • Olivier Ginez, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, et al.. A Concurrent Approach for Testing Address Decoder Faults in eFlash Memories. ITC'07: International Test Conference, paper 3.2, 2007. 〈lirmm-00194260〉
  • Alexandre Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, et al.. Resistive-Open Defect Influences in SRAM I/O Circuitry. Colloque GDR SoC-SiP, France. 2007. 〈lirmm-00194282〉
  • Olivier Ginez, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, et al.. Embedded Flash Testing. Colloque GDR SoC-SiP, France. 2007. 〈lirmm-00194277〉
  • Julien Vial, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel. Test et testabilité de structures numériques tolérantes aux fautes. Colloque GDR SoC-SiP, France. 2007. 〈lirmm-00194278〉
  • Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, et al.. A Mixed Approach for Unified Logic Diagnosis. DDECS'07: IEEE Design and Diagnostics of Electronic Circuits and Systems, Apr 2007, Krakow, Poland, IEEE, pp.239-242, 2007. 〈lirmm-00161643〉
  • Olivier Ginez, Jean-Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, et al.. Electrical Simulation Model of the 2T-FLOTOX Core-Cell for Defect Injection and Faulty Behavior Prediction in eFlash Memories. ETS: European Test Symposium, May 2007, Freiburg, Germany. 12th IEEE European Test Symposium, pp.77-82, 2007, 〈10.1109/ETS.2007.20〉. 〈lirmm-00158543〉
  • Alexandre Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, et al.. Dynamic Two-Cell Incorrect Read Fault due to Resistive-Open Defects in the Sense Amplifiers of SRAMs. ETS: European Test Symposium, May 2007, Freiburg, Germany. 12th IEEE European Test Symposium, pp.97-104, 2007, 〈10.1109/ETS.2007.19〉. 〈lirmm-00158116〉
  • Nabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Christian Landrault, Arnaud Virazel, et al.. Minimizing Peak Power Consumption during Scan Testing: Structural Technique for Don't Care Bits Assignment. IEEE. PRIME'06: Conference on Ph.D. Research in Microelectronics and Electronics, Jun 2006, Otranto, Italy, pp.65-68, 2006. 〈lirmm-00137614〉
  • Nabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Christian Landrault, Arnaud Virazel, et al.. Structural-Based Power-Aware Assignment of Don't Cares for Peak Power Reduction during Scan Testing. VLSI-SOC'06: 14th IFIP WG 10.5 International Conference on Very Large Scale Integration and System-on-Chip, Oct 2006, Nice (France), IEEE, pp.403-408, 2006. 〈lirmm-00108141〉
  • Olivier Ginez, Jean-Michel Daga, Marylène Combe, Patrick Girard, Christian Landrault, et al.. An Overview of Failure Mechanisms in Embedded Flash Memories. VTS'06: VLSI Test Symposium, Apr 2006, Berkeley, CA, United States. IEEE, pp.108-113, 2006. 〈lirmm-00102761〉
  • Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel. Low Power Testing. WRTLT'06: 7th Workshop on RTL and High Level Testing, Nov 2006, Fukuoka, pp.4, 2006. 〈lirmm-00116819〉
  • Nabil Badereddine, Z. Wang, Patrick Girard, K. Chakrabarty, Arnaud Virazel, et al.. Power-Aware Test Data Compression for Embedded IP Core. ATS: Asian Test Symposium, Nov 2006, Fukuoka, Japan. 15th IEEE Asian Test Symposium, pp.5-10, 2006. 〈lirmm-00116832〉
  • Alexandre Rousset, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel. Méthode unifiée de diagnostic ciblant l'ensemble des modèles de fautes. JNRDM: Journées Nationales du Réseau Doctoral de Microélectronique, May 2006, Rennes, France. 9ièmes Journées Nationales du Réseau Doctoral de Microélectronique, 2006. 〈lirmm-00136841〉
  • Alexandre Rousset, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel. Diagnostic Multi-Modèles des Circuits Logiques. MAJECSTIC'06: Manifestation des Jeunes Chercheurs STIC, Nov 2006, Lorient, France. 2006. 〈lirmm-00136876〉
  • Alexandre Rousset, Patrick Girard, Serge Pravossoudovitch, Christian Landrault, Arnaud Virazel. Unified Diagnostic Method Targeting Several Fault Models. VLSI-SOC'06: 14th IFIP WG 10.5 International Conference on Very Large Scale Integration and System-on-Chip, Oct 2006, Nice, pp.53-55, 2006. 〈lirmm-00136869〉
  • Nabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Christian Landrault, Arnaud Virazel, et al.. Technique Structurelle d'Affectation des Bits Non Spécifiés en Vue d'une Réduction de la Puissance de Pic Pendant le Test Série. JNRDM: Journées Nationales du Réseau Doctoral de Microélectronique, May 2006, Rennes, France. 9ièmes Journées Nationales du Réseau Doctoral de Microélectronique, 2006. 〈lirmm-00136838〉
  • Luigi Dilillo, Patrick Girard, Magali Hage-Hassan, Serge Pravossoudovitch, Arnaud Virazel. March Pre: an Efficient Test for Resistive-Open Defects in the SRAM Pre-charge Circuit. DDECS'06: Design and Diagnostics of Electronic Circuits and Systems, Apr 2006, Prague, République Tchèque, IEEE Computer Society Press, pp.256-261, 2006. 〈lirmm-00134776〉
  • Alexandre Rousset, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel. Unified Framework for Logic Diagnosis. IEEE. EWDTW'06: Proceedings of the IEEE East-West Design & Test Workshop, Sep 2006, Sochi, Russia, pp.47-52, 2006. 〈lirmm-00096211〉
  • Olivier Ginez, Jean-Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, et al.. Embedded Flash Testing: Overview and Perspectives. IEEE. DTIS: Design and Technology of Integrated Systems in Nanoscale Era, Sep 2006, Tunis, Tunisia. pp.210-215, 2006. 〈lirmm-00093665〉
  • Nabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Christian Landrault, Arnaud Virazel, et al.. Minimizing Peak Power Consumption during Scan Testing: Test Pattern Modification with X Filling Heuristics. IEEE. DTIS: Design and Technology of Integrated Systems in Nanoscale Era, Sep 2006, Tunis, Tunisia. Design and Technology of Integrated Systems in Nanoscale Era, pp.359-364, 2006. 〈lirmm-00093690〉
  • Nabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Christian Landrault. Why Do We Need to Reduce Peak Power Consumption During Scan Capture?. PATMOS'05: 15th International Workshop on Power and Timing ModelingOptimization and Simulation, Sep 2005, Leuven, Belgium. Springer, pp.540-549, 2005. 〈lirmm-00106111〉
  • Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, B. Hage-Hassan. Test Solutions for Dynamic Faults in SRAM Memories. MEDEA + Design Automation Conference, May 2005, 2005. 〈lirmm-00106558〉
  • Nabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Christian Landrault. Analyse et Réduction de la Puissance de Pic durant le Test Série. JNRDM'05 : 8ièmes Journées Nationales du Réseau Doctoral de Microélectronique, May 2005, Paris, France. 2005. 〈lirmm-00106528〉
  • Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Hage-Hassan. Incidence des Défauts Résistifs dans les Circuits de Précharge des Mémoires SRAM. JNRDM'05 : 8ièmes Journées Nationales du Réseau Doctoral de Microélectronique, May 2005, Paris, France. 2005. 〈lirmm-00106529〉
  • Nabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Christian Landrault, Arnaud Virazel. Peak Power Consumption During Scan Testing: Issue, Analysis and Heuristic Solution. DDECS'05: IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, Apr 2005, Sopron, Hungary. IEEE, pp.151-159, 2005. 〈lirmm-00105990〉
  • Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Mehdi Hage Hassan. Data Retention Fault in SRAM Memories: Analysis and Detection Procedures. VTS'05: 23rd IEEE VLSI Test Symposium, May 2005, Palm Springs, CA (USA), IEEE Computer Society, pp.183-188, 2005. 〈lirmm-00105995〉
  • Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, B. Hage-Hassan. Resistive-Open Defect Influence in SRAM Pre-Charge Circuits: Analysis and Characterization. ETS: European Test Symposium, May 2005, Tallinn, Estonia. 10th IEEE European Test Symposium, pp.116-121, 2005. 〈lirmm-00106010〉
  • Nabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Christian Landrault. Power-Aware Scan Testing for Peak Power Reduction. VLSI-SOC'05: IFIP International Conference on Very Large Scale Integration, Oct 2005, Perth, Australia. pp.441-446, 2005. 〈lirmm-00106112〉
  • Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian. Resistive-Open Defect Injection in SRAM Core-Cell: Analysis and Comparison Between 0.13 um and 90 nm Technologies. DAC: Design Automation Conference, Jun 2005, Anaheim, CA, United States. 42nd Design Automation Conference, pp.857-862, 2005. 〈lirmm-00136906〉
  • Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Hage-Hassan. Efficient Test of Dynamic Read Destructive Faults in SRAM Memories. LATW: Latin American Test Workshop, Mar 2005, Salvador, Bahia, Brazil. 6th IEEE Latin American Test Workshop, pp.40-45, 2005. 〈lirmm-00106515〉
  • Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, S. Borri. March iC-: An Improved Version of March C- for ADOFs Detection. VTS'04: 22nd IEEE VLSI Test Symposium, Apr 2004, Napa Valley, CA (USA), pp.129-134, 2004. 〈lirmm-00108772〉
  • Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, et al.. Test March pour la Détection des Fautes Dynamiques dans les Décodeurs de Mémoires SRAM. JNRDM'04 : 7ièmes Journées Nationales du Réseau Doctoral de Microélectronique, May 2004, Marseille, France. pp.495-497, 2004. 〈lirmm-00108644〉
  • Yannick Bonhomme, Patrick Girard, L. Guiller, Christian Landrault, Serge Pravossoudovitch, et al.. Design of Routing-Constrained Low Power Scan Chains. DELTA: Electronic Design, Test and Applications, Jan 2004, Perth, Australia. IEEE Computer Society, 2nd International Workshop on Electronic Design, Test and Applications, pp.287-292, 2004, 〈10.1109/DELTA.2004.10009〉. 〈lirmm-00108833〉
  • Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, et al.. Dynamic Read Destructive Faults in Embedded-SRAMs: Analysis and March Test Solution. ETS: European Test Symposium, May 2004, Ajaccio, Corsica, France. 9th IEEE European Test Symposium, pp.140-145, 2004. 〈lirmm-00108795〉
  • Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Arnaud Virazel, et al.. Design of Routing-Constrained Low Power Scan Chains. DATE: Design, Automation and Test in Europe, Feb 2004, Paris, France. pp.62-67, 2004, 〈10.1109/DELTA.2004.10009〉. 〈lirmm-00108836〉
  • Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, et al.. March Tests Improvements for Address Decoder Open and Resistive Open Fault Detection. LATW: Latin American Test Workshop, Mar 2004, Cartagena, Colombia. IEEE, 5th IEEE Latin American Test Workshop, pp.31-36, 2004. 〈lirmm-00108642〉
  • Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, et al.. Resistive-Open Defects in Embedded-SRAM Core Cells: Analysis and March Test Solution. ATS: Asian Test Symposium, Nov 2004, Kenting, Taiwan. 13th IEEE Asian Test Symposium, pp.266-271, 2004. 〈lirmm-00108800〉
  • Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, et al.. Comparison of open and resistive-open defect test conditions in SRAM address decoders. ATS: Asian Test Symposium, Nov 2003, Xian, China. 12th IEEE AsianTest Symposium, pp.250-255, 2003, 〈10.1109/ATS.2003.1250818〉. 〈lirmm-01238821〉
  • Simone Borri, Magali Hage-Hassan, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel. Defect-Oriented Dynamic Fault Models for Embedded-SRAMs. ETW: European Test Workshop, May 2003, Maastricht, Netherlands. 8th IEEE European Test Workshop, pp.23-28, 2003. 〈lirmm-00269526〉
  • Patrick Girard, Christian Landrault, Véronique Moreda, Serge Pravossoudovitch, Arnaud Virazel. A BIST Structure to Test Delay Faults in a Scan Environment. ATS: Asian Test Symposium, Dec 1998, Singapore, Singapore. pp.435-439, 1998. 〈lirmm-00345798〉

Poster19 documents

  • Arnaud Virazel, M. Traiolla, Alberto Bosio, Patrick Girardot. A Case Study on the Approximate Test of Integrated Circuits. Colloque GDR SoC-SoC2, Jun 2017, Bordeaux, France. 12ème Colloque du GDR SoC/SiP, 2017. 〈lirmm-01718609〉
  • Arnaud Virazel, Tien Phu Ho, Alberto Bosio, Patrick Girardot. An Advanced Diagnosis Flow for SRAMs. Colloque GDR SoC-SoC2, Jun 2017, Bordeaux, France. 12ème Colloque du GDR SoC/SiP, 2017. 〈lirmm-01718611〉
  • Zhenzhou Sun, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, et al.. Fault-Effect Propagation Based Intra-cell Scan Chain Diagnosis. Colloque GDR SoC-SiP, Jun 2013, Lyon, France. 2013. 〈lirmm-00839113〉
  • João Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, et al.. Performance Evaluation of Capacitive defects on TAS-MRAMs. Colloque GDR SoC-SiP, 2013, Lyon, France. 2013. 〈lirmm-00839093〉
  • Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, et al.. Investigating Multiple-Cell-Upsets on a 90mn SRAM. Colloque GDR SoC-SiP, 2013, Lyon, France. 2013. 〈lirmm-00839108〉
  • João Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, et al.. Coupling-Based Resistive-Open Defects in TAS-MRAM Architectures. ETS: European Test Symposium, May 2012, Annecy, France. Test Symposium (ETS), 2012 17th IEEE European, 2012, 〈10.1109/ETS.2012.6233034〉. 〈lirmm-00806793〉
  • Carolina Metzler, Aida Todri-Sanial, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, et al.. Resistive Open Defect Analysis for Through-Silicon-Vias. ETS: European Test Symposium, May 2012, Annecy, France. 17th IEEE European Test Symposium, pp.183, 2012. 〈lirmm-00806795〉
  • Ahn Duc Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, et al.. Parity Prediction Synthesis for Nano-Electronic Gate Designs. ITC'2010: International Test Conference, Nov 2010, Austin, Texas, United States. pp.N/A, 2010. 〈lirmm-00537938〉
  • Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, et al.. Is Test Power Reduction Through X-Filling Good Enough?. ITC'2010: International Test Conference, Nov 2010, Austin, Texas, United States. 2010. 〈lirmm-00537926〉
  • Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, et al.. SRAM Core-cell Quality Metrics. GDR SOC SIP, France. 2009. 〈lirmm-00434962〉
  • Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, et al.. Trade-off Between Power Dissipation and Delay Fault Coverage for LOS and LOC Testing Schemes. GDR SOC SIP, France. 2009. 〈lirmm-00434959〉
  • Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, et al.. NAND Flash Testing: A Preliminary Study on Actual Defects. ITC'2009: International Test Conference, Nov 2009, Austin, Texas, United States. pp.13, 2009. 〈lirmm-00433765〉
  • Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, et al.. Test des Mémoires FLASH NAND. Colloque GDR SoC-SiP, France. 2009. 〈lirmm-00433770〉
  • Youssef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, et al.. A Logic Diagnosis Approach for Sequential Circuits. IEEE European Test Symposium'09, Ph. D. Forum, Spain. 2009. 〈lirmm-00433792〉
  • Julien Vial, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, et al.. SoC Yield Improvement for Future Nanoscale Technologies. European Test Symposium. PhD Forum, Spain. 2009. 〈lirmm-00433798〉
  • Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, et al.. Analysis of Resistive-Bridging Defects in SRAM Core-Cell: Impact within the Core-Cell and in the Memory Array. ETS: European Test Symposium, May 2009, Sevilla, Spain. 14th IEEE European Test Symposium, 2009. 〈lirmm-00433796〉
  • Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, et al.. SoC Yield Improvement: Redundant Architectures to the Rescue. ITC'2008: International Test Conference, Oct 2008, Santa Clara, CA, United States. IEEE, pp.7, 2008. 〈lirmm-00341799〉
  • Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian. Failure Mechanisms due to Process Variations in Nanoscale SRAM Core-Cells. ETS: European Test Symposium, May 2006, Southampton, United Kingdom. 11th IEEE European Test Symposium, 2006. 〈lirmm-00134787〉
  • Christian Landrault, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine, et al.. Structural Power-Aware Assignment of Xs for Peak Power Reduction during Scan Testing. ETS: European Test Symposium, May 2006, Southampton, United Kingdom. 11th IEEE European Test Symposium, 2006. 〈lirmm-00134781〉

Ouvrage (y compris édition critique et traduction)1 document

  • Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel. Advanced Test Methods for SRAMs - Effective Solutions for Dynamic Fault Detection in Nanoscaled Technologies. Springer, 171 p., 2009, 978-1-4419-0937-4. 〈lirmm-00371359〉

Chapitre d'ouvrage2 documents

  • Yuanqing Cheng, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, et al.. Electromigration Alleviation Techniques for 3D Integrated Circuits. Chao Wang. High Performance Computing for Big Data: Methodologies and Applications, CRC Press 2017, pp.37-58, 2017, 9781498783996. 〈lirmm-01800220〉
  • Nabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Christian Landrault. Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles. VLSI-Soc: From Systems to Silicon, pp.267-281, 2007, 978-0-387-73661-7. 〈lirmm-00194261〉

Autre publication11 documents

  • Arnaud Virazel, Tien Phu Ho, Alberto Bosio, Patrick Girard. An Advanced Diagnosis Flow using CustomSim for SRAMs. Synopsys User Group Conference. 2017. 〈lirmm-01718615〉
  • Patrick Girard, Serge Bernard, Florence Azaïs, Alberto Bosio, Luigi Dilillo, et al.. Rapport Technique intermédiaire, Contrat TOETS CT 302, Programme CEE CATRENE. 2011. 〈lirmm-00679018〉
  • Patrick Girard, Serge Bernard, Florence Azaïs, Alberto Bosio, Luigi Dilillo, et al.. Rapport Technique de fin d'année, Contrat TOETS CT 302, Programme CEE CATRENE. 2011. 〈lirmm-00679022〉
  • Patrick Girard, Florence Azaïs, Serge Bernard, Alberto Bosio, Luigi Dilillo, et al.. TOETS CT302 - Programme CEE CATRENE - Summary Technical Report 2S-2009 - Rapport Technique de Fin d'année. 2010. 〈lirmm-00461745〉
  • Patrick Girard, Serge Bernard, Florence Azaïs, Alberto Bosio, Luigi Dilillo, et al.. Contrat TOETS CT 302 - Programme CEE CATRENE (Rapport Intermédiaire). 2010. 〈lirmm-00504873〉
  • Patrick Girard, Serge Bernard, Alberto Bosio, Luigi Dilillo, Marie-Lise Flottes, et al.. Rapport Technique de fin de Contrat NanoTEST 2A702, Programme CEE MEDEA+. 2009. 〈lirmm-00406974〉
  • Patrick Girard, Serge Bernard, Alberto Bosio, Marie-Lise Flottes, Serge Pravossoudovitch, et al.. Contrat NanoTEST 2A702 - Programme CEE MEDEA - Rapport Technique intermédiaire. 2007. 〈lirmm-00199966〉
  • Patrick Girard, Serge Bernard, Alberto Bosio, Marie-Lise Flottes, Serge Pravossoudovitch, et al.. Contrat NanoTEST 2A702 - Programme CEE MEDEA - Rapport Technique de fin d'année. 2007. 〈lirmm-00199958〉
  • Patrick Girard, Serge Bernard, Marie-Lise Flottes, Christian Landrault, Serge Pravossoudovitch, et al.. Contrat NanoTEST 2A702, Programme CEE MEDEA +. 2006. 〈lirmm-00130759〉
  • Patrick Girard, Serge Bernard, Marie-Lise Flottes, Christian Landrault, Serge Pravossoudovitch, et al.. Contrat NanoTEST 2A702 - Programme CEE MEDEA+. 12927. 2006. 〈lirmm-00102699〉
  • Patrick Girard, Serge Bernard, Marie-Lise Flottes, Christian Landrault, Serge Pravossoudovitch, et al.. Contrat NanoTEST 2A702, Programme CEE MEDEA+. 2006. 〈lirmm-00130758〉

Rapport2 documents

  • Patrick Girard, Serge Bernard, Alberto Bosio, Marie-Lise Flottes, Serge Pravossoudovitch, et al.. Contrat Nano TEST 2A702, Programme CEE MEDEA (Rapport Technique de fin d'année). 08026, 2008. 〈lirmm-00344408〉
  • Patrick Girard, Serge Bernard, Alberto Bosio, Marie-Lise Flottes, Serge Pravossoudovitch, et al.. Contrat Nano TEST 2A702, Programme CEE MEDEA (Rapport Intermédiaire). 08027, 2008. 〈lirmm-00344415〉

HDR1 document

  • Arnaud Virazel. Contribution au test et à la fiabilité des systèmes sur puce. Micro et nanotechnologies/Microélectronique. Université Montpellier 2, 2014. 〈tel-01420363〉