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148 résultats
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Selecting Benchmark Combinations for the Evaluation of Multicore ThroughputInternational Symposium on Performance Analysis of Systems and Software, Apr 2013, Austin, United States. ⟨10.1109/ISPASS.2013.6557168⟩
Communication dans un congrès
hal-00788824v1
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GCDS: A Compiler Strategy for Trading Code Size Against Performance in Embedded Applications[Research Report] RR-3346, INRIA. 1998
Rapport
inria-00073343v1
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Understanding cache attacks[Research Report] RR-5881, INRIA. 2006
Rapport
inria-00071387v1
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CASH Design Space Exploration[Research Report] RR-5994, INRIA. 2006
Rapport
inria-00105284v3
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Don't Use the Page Number, but a Pointer on It[Research Report] RR-2727, INRIA. 1995
Rapport
inria-00073967v1
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Évolution des gammes de processeurs MIPS, DEC Alpha, PowerPC, SPARC, x86 et PA-RISC[Rapport de recherche] RR-3188, INRIA. 1997
Rapport
inria-00073501v1
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SIMT-X: Extending Single-Instruction Multi-Threading to Out-of-Order CoresACM Transactions on Architecture and Code Optimization, 2020, 17 (2), pp.15. ⟨10.1145/3392032⟩
Article dans une revue
hal-02542333v1
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The FNL+MMA Instruction Cache PrefetcherIPC-1 - First Instruction Prefetching Championship, May 2020, Valence, Spain. pp.1-5
Communication dans un congrès
hal-02884880v1
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Decoupled Zero-Compressed MemoryHiPEAC - International Conference on High-Performance and Embedded Architectures and Compilers, Jan 2011, Heraklion, Greece. ⟨10.1145/1944862.1944876⟩
Communication dans un congrès
inria-00529332v1
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Fairness Metrics for Multithreaded ProcessorsIEEE Computer Architecture Letters, 2011, IEEE Computer Architecture Letters 2011, ⟨10.1109/L-CA.2011.1⟩
Article dans une revue
inria-00564560v1
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TAGE-SC-L Branch PredictorsJILP - Championship Branch Prediction, Jun 2014, Minneapolis, United States
Communication dans un congrès
hal-01086920v1
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Practical Multidimensional Branch PredictionIEEE Micro, 2016, ⟨10.1109/MM.2016.33⟩
Article dans une revue
hal-01330510v1
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Les processeurs multicœurs aujourd’hui et demainInterstices, 2011
Article dans une revue
hal-01350165v1
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Cost Effective Physical Register SharingInternational Symposium on High Performance Computer Architecture, IEEE, Mar 2016, Barcelona, Spain. ⟨10.1109/HPCA.2016.7446105⟩
Communication dans un congrès
hal-01259137v2
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Dictionary Sharing: An Efficient Cache Compression Scheme for Compressed Caches MICRO 2016 - 49th Annual IEEE/ACM International Symposium on Microarchitecture, IEEE/ACM, Oct 2016, Taipei, Taiwan
Communication dans un congrès
hal-01354246v3
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Managing SMT Resource Usage through Speculative Instruction Window Weighting[Research Report] RR-7103, INRIA. 2009, pp.22
Rapport
inria-00433081v2
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Storage Free Confidence Estimation for the TAGE branch predictor[Research Report] RR-7371, INRIA. 2010, pp.20
Rapport
inria-00512130v2
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Managing SMT resource usage through speculative instruction window weightingACM Transactions on Architecture and Code Optimization, 2011, ⟨10.1145/2019608.2019611⟩
Article dans une revue
hal-00639171v1
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Performance Upper Bound Analysis and Optimization of SGEMM on Fermi and Kepler GPUsCGO '13 - 2013 International Symposium on Code Generation and Optimization, Feb 2013, Shenzhen, China
Communication dans un congrès
hal-00789958v1
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Efficient Out-of-Order Execution of Guarded ISAsACM Transactions on Architecture and Code Optimization, 2014, pp.21. ⟨10.1145/2677037⟩
Article dans une revue
hal-01103230v1
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Zero-Content Augmented CachesICS 2009 : 23rd International Conference on Supercomputing, Jun 2009, New York, United States. ⟨10.1145/1542275.1542288⟩
Communication dans un congrès
inria-00374524v1
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Register Sharing for Equality PredictionInternational Symposium on Microarchitecture, Oct 2016, Taipei, Taiwan
Communication dans un congrès
hal-01354267v1
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SALTO : System for Assembly-Language Transformation and Optimization[Research Report] RR-2980, INRIA. 1996
Rapport
inria-00073718v1
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About Effective Cache Miss Penalty on Out-of-Order Superscalar Processors[Research Report] RR-2726, INRIA. 1995
Rapport
inria-00073968v1
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Etude Comparative des Architectures des Microprocesseurs Intel Pentium et PowerPC 601[Rapport de recherche] RR-2320, INRIA. 1994
Rapport
inria-00074354v1
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CASH: Revisiting hardware sharing in single-chip parallel processor[Research Report] RR-4660, INRIA. 2002
Rapport
inria-00071925v1
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Compressed cache layout aware prefetchingSBAC-PAD 2019 - International Symposium on Computer Architecture and High Performance Computing, Oct 2019, Campo Grande, MS, Brazil. pp.1-4
Communication dans un congrès
hal-02316773v1
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Understanding Cache CompressionACM Transactions on Architecture and Code Optimization, 2021, 18 (3), pp.1-27. ⟨10.1145/3457207⟩
Article dans une revue
hal-03285041v1
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OPAC : a floating-point coprocessor dedicated to compute-bound kernels[Research Report] RR-1555, INRIA. 1991
Rapport
inria-00075006v1
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Zero-Content Augmented Caches[Research Report] RR-6705, INRIA. 2008
Rapport
inria-00337742v1
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