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Amer BAGHDADI
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Documents
Identifiants chercheurs
amer-baghdadi-
0000-0002-6181-6500
- IdRef : 067318398
Présentation
**Amer Baghdadi** is a Professor at IMT Atlantique. He received his Engineering degree in 1998, Master of Science degree in the same year and PhD degree in 2002, all from Grenoble INP (Institut National Polytechnique), France. Furthermore, he received the accreditation to supervise research (HDR) in Sciences and Technologies of Information and Communication in 2012 from the University of Southern Brittany, France.
His general technical area concerns both theoretical and practical aspects, and both algorithm development for digital baseband components and corresponding hardware/software implementations and digital circuit design. His research activities target mainly digital communication applications, in addition to other application domains, and more particularly the design of flexible digital physical layer for future wireless communication standards and terminals. Prof. Baghdadi is IEEE Senior Member. He serves on the technical program committee for several international conferences. He co-authored more than 100 papers on scientific journals and proceedings of international conferences.
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NISC Design Experience of Flexible Architectures for Digital Communication ApplicationsICCA 2018 : International Conference on Computer and Applications, Aug 2018, Beirut, Lebanon. pp.123-129, ⟨10.1109/COMAPP.2018.8460355⟩
Communication dans un congrès
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Implementation of NISC-based flexible architecture for MIMO MMSE-IC turbo-equalizationJNRDM 2014 : 17èmes Journées Nationales du Réseau Doctoral en Micro-Nanoélectronique,, May 2014, Lille, France
Communication dans un congrès
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Design and prototyping flow of NISC-based flexible MIMO turbo-equalizerRSP 2014 : IEEE International Symposium on Rapid System Prototyping, Oct 2014, New Delhi, India. pp.16 - 21, ⟨10.1109/RSP.2014.6966687⟩
Communication dans un congrès
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Flexible and efficient architecture design for MIMO MMSE-IC linear turbo-equalizationICCIT 2013 : 3rd IEEE International Conference on Communications and Information Technology, Jun 2013, Beirut, Lebanon. pp.340 - 344, ⟨10.1109/ICCITechnology.2013.6579576⟩
Communication dans un congrès
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Designing a NISC-based flexible architecture for MIMO MMSE-IC turbo-equalizationJNRDM 2013 : 16èmes Journées Nationales du Réseau Doctoral en Micro-Nanoélectronique, Jun 2013, Grenoble, France
Communication dans un congrès
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Statically-scheduled application-specific processor design: A case-study on MMSE MIMO equalizationDATE 2013 : IEEE/ACM Design, Automation & Test in Europe Conference & Exhibition, Mar 2013, Grenoble, France. pp.677 - 680
Communication dans un congrès
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Quantization and fixed-point arithmetic for MIMO MMSE-IC linear turbo-equalizationICM 2013 : 25th IEEE International Conference on MicroelectronicsMicroelectronics, Dec 2013, Beirut, Lebanon. pp.1 - 4, ⟨10.1109/ICM.2013.6735008⟩
Communication dans un congrès
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Rapid Design and Prototyping of a Reconfigurable Decoder Architecture for QC-LDPC CodesRSP 2013 : 24th IEEE International Symposium on Rapid System Prototyping, Oct 2013, Montreal, Canada
Communication dans un congrès
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Parameterized area-efficient multi-standard turbo decoderDATE 2013 : IEEE/ACM Design, Automation & Test in Europe Conference & Exhibition, Mar 2013, Grenoble, France. pp.109 - 114
Communication dans un congrès
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Convergence and Complexity Analysis of Turbo Demodulation with Turbo DecodingColloque national du groupe de recherches System On Chip - System In Package (SOC-SIP), Jun 2012, Paris, France
Communication dans un congrès
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Adaptive Complexity MIMO Turbo Receiver Applying Turbo DemodulationISTC 2012: 7th International Symposium on International Symposium onTurbo Codes and Iterative Information Processing, Aug 2012, Gothenburg, Sweden. pp.235 - 239
Communication dans un congrès
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Complexity reduction of shuffled parallel iterative demodulation with turbo decodingICT 2012: 19th International Conference on Telecommunications, Apr 2012, Jounieh, Lebanon. ⟨10.1109/ICTEL.2012.6221298⟩
Communication dans un congrès
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Architecture Efficiency of Application-Specific Processors: a 170Mbit/s 0.644mm2 Multi-standard Turbo DecoderSOC 2012 IEEE International Symposium on System-on-Chip, Oct 2012, Tampere, Finland
Communication dans un congrès
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FPGA Prototyping and Performance Evaluation of Multi-standard Turbo/LDPC Encoding and DecodingRSP 2012: IEEE International Symposium on Rapid System Prototyping, Oct 2012, Tampere, Finland
Communication dans un congrès
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Flexible Multi-ASIP SoC for Turbo/LDPC DecoderSOC-SIP : colloque national du groupe de recherches System On Chip - System In Package, Jun 2012, Paris, France
Communication dans un congrès
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A low complexity stopping criterion for reducing power consumption in turbo decodersDATE'11: IEEE/ACM Design, Automation and Test in Europe Conference & Exhibition, Mar 2011, Grenoble, France. pp.1530 - 1591
Communication dans un congrès
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Area and throughput optimized ASIP for multi-standard turbo decodingRSP 2011: 22nd IEEE International Symposium on Rapid System Prototyping, May 2011, Karlsruhe, Allemagne. pp.79 - 84, ⟨10.1109/RSP.2011.5929979⟩
Communication dans un congrès
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FPGA Prototype of Flexible Heterogeneous multi-ASIP NoC-based Unified Turbo ReceiverDATE 2011: Demonstration at the University Booth of the Design, Automation and Test in Europe Conference & Exhibition, Mar 2011, Grenoble, France
Communication dans un congrès
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Reducing the number of iterations in iterative demodulation with turbo decodingSoftCOM : International Conference on Software, Telecommunications and Computer Networks, Sep 2011, Split, Croatia
Communication dans un congrès
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A flexible high throughput multi-ASIP architecture for LDPC and turbo decodingDATE'11: IEEE/ACM Design, Automation and Test in Europe Conference & Exhibition, Mar 2011, Grenoble, France
Communication dans un congrès
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Rapid design and prototyping of universal soft demapperISCAS : IEEE International Symposium on Circuits and Systems, May 2010, Paris, France
Communication dans un congrès
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TurbASIP power consumption analysis and optimizationColloque national du groupe de recherches System On Chip - System In Package (SOC-SIP), Jun 2010, Paris, France
Communication dans un congrès
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Exploring parallel processing levels in turbo demodulationInternational Symposium on Turbo Codes and Iterative Information Processing, Sep 2010, Brest, France. pp.359 - 363, ⟨10.1109/ISTC.2010.5613904⟩
Communication dans un congrès
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DemASIP : universal demapper for multiwireless standardsColloque national du groupe de recherches "System On Chip - System In Package" (SOC-SIP), Jun 2010, Paris, France
Communication dans un congrès
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Power consumption analysis and energy efficient optimization for turbo decoder implementationInternational Symposium on System-on-Chip, Sep 2010, Tampere, Finland. pp.12 - 17, ⟨10.1109/ISSOC.2010.5625565⟩
Communication dans un congrès
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Flexible architectures for LDPC decoders based on network on chip paradigmDSD 2009 : 12th Euromicro Conference on Digital System Design, Sep 2009, Patras, Greece
Communication dans un congrès
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Rapid prototyping of ASIP-based flexible MMSE-IC linear equalizerRSP09 : IEEE International Symposium on Rapid System Prototyping, Jun 2009, Paris, France. pp.130-133, ⟨10.1109/RSP.2009.17⟩
Communication dans un congrès
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FPGA prototypes for turbo communication applicationsUniversity Booth of DATE 09 : Design, Automation & Test in Europe Conference & Exhibition, Apr 2009, Nice, France
Communication dans un congrès
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ASIP-based flexible MMSE-IC linear equalizer for MIMO turbo-equalization applicationsDATE09 : Design, Automation & Test in Europe Conference & Exhibition, Apr 2009, Nice, France
Communication dans un congrès
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On-chip communication network for flexible multiprocessor turbo decodingICTTA '08 : 3d International Conference on Information and Communication Technologies : From Theory to Applications, Apr 2008, Damas, Syria. pp.1 - 6
Communication dans un congrès
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From application to ASIP-based FPGA prototype : a case study on turbo decodingRSP'2008 : the 19th IEEE/IFIP international symposium on rapid system prototyping, Jun 2008, Monterey, United States. pp.128 - 134, ⟨10.1109/RSP.2008.16⟩
Communication dans un congrès
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Binary de Bruijn on-chip network for a flexible multiprocessor LDPC decoderDAC 2008 : 45th ACM/IEEE design automation conference, Jun 2008, Anaheim, United States. pp.429 - 434, ⟨10.1109/DAC.2008.4555856⟩
Communication dans un congrès
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Binary de Bruijn interconnection network for a flexible LDPC/turbo decoderIEEE International Symposium on Circuits and Systems (ISCAS 2008), May 2008, Seattle, WA, United States. pp.97-100, ⟨10.1109/ISCAS.2008.4541363⟩
Communication dans un congrès
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Flexible and scalable on-chip communication network for multiprocessor turbo decodingPremier Colloque National du GDR SOC-SIP, Jun 2007, Paris, France
Communication dans un congrès
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Flexible Multi-ASIP SoC for High-Throughput Turbo DecodersPremier Colloque National du GDR SOC-SIP, Jun 2007, Paris, France
Communication dans un congrès
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Butterfly and benes-based on-chip communication networks for multiprocessor turbo decodingDATEC 2007 : Design, Automation & Test in Europe Conference & Exhibition, Apr 2007, Nice, France. pp.654 - 659
Communication dans un congrès
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On the parallelism of convolutional turbo decoding and interleaving interferenceGLOBECOM 2006 : 49th annual Global telecommunications conference, Nov 2006, San Francisco, United States. pp.1 - 5, ⟨10.1109/GLOCOM.2006.558⟩
Communication dans un congrès
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ASIP-based multiprocessor SoC design for simple and double binary turbo decodingDATE 06 : Design, Automation and Test in Europe, Mar 2006, Munich, Germany. pp.1 - 6, ⟨10.1109/DATE.2006.244126⟩
Communication dans un congrès
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Exploring parallel processing levels for convolutional turbo decodingICCTA'06 : IEEE International Conference on Information and Communication Technologies : from theory to applications, April 24-28, Damas, Syria, Apr 2006, Damas, Syria. pp.2353 - 2358
Communication dans un congrès
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Parallélisme et turbocodes convolutifsMajecSTIC 2006 : MAnifestation des JEunes Cherchercheurs STIC, Nov 2006, Lorient, France
Communication dans un congrès
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Designing a NISC-based flexible architecture for MIMO MMSE-IC turbo-equalizationJNRDM 2013 : 16èmes Journées Nationales du Réseau Doctoral en Micro-Nanoélectronique, Jun 2013, Grenoble, France. 2013
Poster de conférence
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Application-Specific Processor Design: a Case-Study on MMSE MIMO equalizationGDR SoC-SiP 2013 : Colloque National du Groupe de Recherche System on Chip -System in Package, Jun 2013, Lyon, France. 2013
Poster de conférence
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ASIP Design for Multi-Standard Channel DecodersAdvanced Hardware Design for Error Correcting Codes, Springer, pp.151 - 175, 2014, 978-3-319-10568-0. ⟨10.1007/978-3-319-10569-7⟩
Chapitre d'ouvrage
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ASIP design and prototyping for wireless communication applicationsAdvanced Applications of Rapid Prototyping Technology in Modern Engineering, InTech - Open Access Publisher, 2011
Chapitre d'ouvrage
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