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Amer BAGHDADI
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Documents
Identifiants chercheurs
amer-baghdadi-
0000-0002-6181-6500
- IdRef : 067318398
Présentation
**Amer Baghdadi** is a Professor at IMT Atlantique. He received his Engineering degree in 1998, Master of Science degree in the same year and PhD degree in 2002, all from Grenoble INP (Institut National Polytechnique), France. Furthermore, he received the accreditation to supervise research (HDR) in Sciences and Technologies of Information and Communication in 2012 from the University of Southern Brittany, France.
His general technical area concerns both theoretical and practical aspects, and both algorithm development for digital baseband components and corresponding hardware/software implementations and digital circuit design. His research activities target mainly digital communication applications, in addition to other application domains, and more particularly the design of flexible digital physical layer for future wireless communication standards and terminals. Prof. Baghdadi is IEEE Senior Member. He serves on the technical program committee for several international conferences. He co-authored more than 100 papers on scientific journals and proceedings of international conferences.
Publications
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A reconfigurable multi-standard ASIP-based turbo decoder for an efficient dynamic reconfiguration in a multi-ASIPISVLSI 2013 : IEEE Computer Society Annual Symposium on VLSI, Aug 2013, Natal, Brazil. ⟨10.1109/ISVLSI.2013.6654620⟩
Communication dans un congrès
hal-01002828v1
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Optimizations for an efficient reconfiguration of an ASIP-based turbo decoderISCAS 2013 : IEEE International Symposium on Circuits and Systems, May 2013, Beijing, Chine. pp.493 - 496, ⟨10.1109/ISCAS.2013.6571888⟩
Communication dans un congrès
hal-00873979v1
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FPGA Prototyping and Performance Evaluation of Multi-standard Turbo/LDPC Encoding and DecodingRSP 2012: IEEE International Symposium on Rapid System Prototyping, Oct 2012, Tampere, Finland
Communication dans un congrès
hal-00797561v1
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Flexible Multi-ASIP SoC for Turbo/LDPC DecoderSOC-SIP : colloque national du groupe de recherches System On Chip - System In Package, Jun 2012, Paris, France
Communication dans un congrès
hal-00725184v1
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Efficient dynamic configuration of a multi-ASIP turbo decoderGDR SoC-SiP 2013 : Colloque National du Groupe de Recherche System on Chip -System in Package, Jun 2013, Lyon, France
Poster de conférence
hal-00876017v1
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