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Amer BAGHDADI
168
Documents
Identifiants chercheurs
- amer-baghdadi
- 0000-0002-6181-6500
- IdRef : 067318398
Présentation
**Amer Baghdadi** is a Professor at IMT Atlantique. He received his Engineering degree in 1998, Master of Science degree in the same year and PhD degree in 2002, all from Grenoble INP (Institut National Polytechnique), France. Furthermore, he received the accreditation to supervise research (HDR) in Sciences and Technologies of Information and Communication in 2012 from the University of Southern Brittany, France.
His general technical area concerns both theoretical and practical aspects, and both algorithm development for digital baseband components and corresponding hardware/software implementations and digital circuit design. His research activities target mainly digital communication applications, in addition to other application domains, and more particularly the design of flexible digital physical layer for future wireless communication standards and terminals. Prof. Baghdadi is IEEE Senior Member. He serves on the technical program committee for several international conferences. He co-authored more than 100 papers on scientific journals and proceedings of international conferences.
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Shared resources high-level modeling in embedded systems using virtual nodesJoint IEEE North-East Workshop on Circuits and Systems and TAISA Conference 2009, Jun 2009, Toulouse, France. ⟨10.1109/NEWCAS.2009.5290506⟩
Communication dans un congrès
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FPGA-based radar signal processing for automotive driver assistance systemRSP09 : IEEE/IFIP International Symposium on Rapid System Prototyping,, Jun 2009, Paris, France. pp.196-199, ⟨10.1109/RSP.2009.26⟩
Communication dans un congrès
hal-00424189v1
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ASIP-based flexible MMSE-IC linear equalizer for MIMO turbo-equalization applicationsDATE09 : Design, Automation & Test in Europe Conference & Exhibition, Apr 2009, Nice, France
Communication dans un congrès
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High-level system modeling for rapid HW/SW architecture explorationIEEE/IFIP International Symposium on Rapid System Prototyping (RSP '09), Jun 2009, Paris, France. pp.88-94, ⟨10.1109/RSP.2009.27⟩
Communication dans un congrès
hal-02124754v1
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Flexible architectures for LDPC decoders based on network on chip paradigmDSD 2009 : 12th Euromicro Conference on Digital System Design, Sep 2009, Patras, Greece
Communication dans un congrès
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From application to ASIP-based FPGA prototype : a case study on turbo decodingRSP'2008 : the 19th IEEE/IFIP international symposium on rapid system prototyping, Jun 2008, Monterey, United States. pp.128 - 134, ⟨10.1109/RSP.2008.16⟩
Communication dans un congrès
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Architectures des systèmes numériques de traitement : de l'électronique à l'informatique10èmes journées pédagogiques du CNFM (Coordination nationale de la formation en micro et nanoélectronique), Nov 2008, Saint Malo, France
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On-chip communication network for flexible multiprocessor turbo decodingICTTA '08 : 3d International Conference on Information and Communication Technologies : From Theory to Applications, Apr 2008, Damas, Syria. pp.1 - 6
Communication dans un congrès
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Binary de Bruijn on-chip network for a flexible multiprocessor LDPC decoderDAC 2008 : 45th ACM/IEEE design automation conference, Jun 2008, Anaheim, United States. pp.429 - 434, ⟨10.1109/DAC.2008.4555856⟩
Communication dans un congrès
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Binary de Bruijn interconnection network for a flexible LDPC/turbo decoderIEEE International Symposium on Circuits and Systems (ISCAS 2008), May 2008, Seattle, WA, United States. pp.97-100, ⟨10.1109/ISCAS.2008.4541363⟩
Communication dans un congrès
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Millimetre communication system for IVCITST 2007 : 7th International Conference on ITS (Intelligent Transport Systems), Jun 2007, Sophia-Antipolis, France. ⟨10.1109/ITST.2007.4295879⟩
Communication dans un congrès
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Flexible Multi-ASIP SoC for High-Throughput Turbo DecodersPremier Colloque National du GDR SOC-SIP, Jun 2007, Paris, France
Communication dans un congrès
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Flexible and scalable on-chip communication network for multiprocessor turbo decodingPremier Colloque National du GDR SOC-SIP, Jun 2007, Paris, France
Communication dans un congrès
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Butterfly and benes-based on-chip communication networks for multiprocessor turbo decodingDATEC 2007 : Design, Automation & Test in Europe Conference & Exhibition, Apr 2007, Nice, France. pp.654 - 659
Communication dans un congrès
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Parallélisme et turbocodes convolutifsMajecSTIC 2006 : MAnifestation des JEunes Cherchercheurs STIC, Nov 2006, Lorient, France
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Exploring parallel processing levels for convolutional turbo decodingICCTA'06 : IEEE International Conference on Information and Communication Technologies : from theory to applications, April 24-28, Damas, Syria, Apr 2006, Damas, Syria. pp.2353 - 2358
Communication dans un congrès
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ASIP-based multiprocessor SoC design for simple and double binary turbo decodingDATE 06 : Design, Automation and Test in Europe, Mar 2006, Munich, Germany. pp.1 - 6, ⟨10.1109/DATE.2006.244126⟩
Communication dans un congrès
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On the parallelism of convolutional turbo decoding and interleaving interferenceGLOBECOM 2006 : 49th annual Global telecommunications conference, Nov 2006, San Francisco, United States. pp.1 - 5, ⟨10.1109/GLOCOM.2006.558⟩
Communication dans un congrès
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On the Flexibility and Scalability of Multiprocessor Embedded System Design for Emerging In-Vehicle Applications5th International Conference on ITS Telecommunications, Jun 2005, Brest, France
Communication dans un congrès
hal-02137868v1
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An efficient scalable and flexible data transfer architecture for multiprocessor SoC with massive distributed memorySan Diego, CA, 2004, San Diego, United States. pp.250-5, ⟨10.1145/996566.996636⟩
Communication dans un congrès
hal-00008046v1
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An Efficient Architecture for the Implementation of Message Passing Programming Model on Massive Multiprocessor SoC15th IEEE International Workshop on Rapid System Prototyping, Jun 2004, Genève, Suisse
Communication dans un congrès
hal-02138091v1
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An efficient architecture for the implementation of message passing programming model on massive multiprocessorRSP 2004 : 15th IEEE International Workshop on Rapid System Prototyping, Jun 2004, Genève, Switzerland. pp.80-7
Communication dans un congrès
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Embedded application prototyping on a communication-restricted reconfigurable platformIWRSP 2003 : 14th IEEE International Workshop on Rapid Systems Prototyping, Jun 2003, San Diego, United States. pp.33-9, ⟨10.1109/IWRSP.2003.1207027⟩
Communication dans un congrès
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Component-based design approach for multicore SoCs2002 Design Automation Conference, Jun 2002, New Orleans, United States. pp.789-94, ⟨10.1109/DAC.2002.1012730⟩
Communication dans un congrès
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HW/SW interfaces design of a VDSL modem using automatic refinement of a virtual architecture specification into a multiprocessor SoC: a case studyDesign, Automation and Test in Europe (DATE'02), Mar 2002, Paris, France
Communication dans un congrès
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Exploration et conception systématique d'architectures multiprocesseurs monopuces dédiées à des applications spécifiques3ème Colloque CAO de circuits et systèmes intégrés, May 2002, Paris, France
Communication dans un congrès
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An efficient architecture model for systematic design of application-specific multiprocessor SoCDATE 2001 : Design, Automation and Test in Europe. Conference and Exhibition., Mar 2001, Munich, Germany. pp.55-62, ⟨10.1109/DATE.2001.915001⟩
Communication dans un congrès
hal-00008086v1
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A generic wrapper architecture for multi-processor SoC cosimulation and designCODES '01 : Ninth international symposium on Hardware/software codesign, 2001, Copenhague, Denmark. pp.195-200, ⟨10.1145/371636.371722⟩
Communication dans un congrès
hal-00008087v1
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Automatic generation of application-specific architectures for heterogeneous multiprocessor system-on-chipDAC '01 : 38th annual Design Automation Conference, 2001, Las Vegas, United States. pp.518-23, ⟨10.1145/378239.379015⟩
Communication dans un congrès
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Application-specific multiprocessor systems-on-chipThe Tenth Workshop on Synthesis And System Integration of Mixed Technologies (SASIMI'01), Oct 2001, Nara, Japan
Communication dans un congrès
hal-01391627v1
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Generic architecture platform for multiprocessor system-on-chip designDIPES 2000: Architecture and Design of Distributed Embedded Systems, Oct 2000, Schloß Eringerfeld, Germany. pp.53-63
Communication dans un congrès
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Design space exploration for hardware/software codesign of multiprocessor systemsRSP 2000 : 11th International Workshop on Rapid System Prototyping, Jun 2000, Paris, France. pp.8-13, ⟨10.1109/IWRSP.2000.854975⟩
Communication dans un congrès
hal-00008096v1
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Generic architecture platform for multiprocessor embedded system-on-chip designInternational Workshop on Distributed and Parallel Embedded Systems (DIPES'00), Oct 2000, Paderborn, Allemagne. pp.53-64
Communication dans un congrès
hal-01381242v1
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Framework for system design, validation and fast prototyping of multiprocessor system-on-chip: applied to telecommunication systemsInternational Workshop on Distributed and Parallel Embedded Systems (DIPES'00), Jan 2000, Paderborn, Allemagne
Communication dans un congrès
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Key Attack Strategies Against Black-Box DNNsPoster de conférence hal-03690454v1 |
Flexible FBMC air interface for 5GMWC 2015 : Mobile World Congress, Mar 2015, Barcelona, Spain. 2015
Poster de conférence
hal-01170210v1
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Efficient dynamic configuration of a multi-ASIP turbo decoderGDR SoC-SiP 2013 : Colloque National du Groupe de Recherche System on Chip -System in Package, Jun 2013, Lyon, France
Poster de conférence
hal-00876017v1
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Designing a NISC-based flexible architecture for MIMO MMSE-IC turbo-equalizationJNRDM 2013 : 16èmes Journées Nationales du Réseau Doctoral en Micro-Nanoélectronique, Jun 2013, Grenoble, France. 2013
Poster de conférence
hal-00876046v1
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Application-Specific Processor Design: a Case-Study on MMSE MIMO equalizationGDR SoC-SiP 2013 : Colloque National du Groupe de Recherche System on Chip -System in Package, Jun 2013, Lyon, France. 2013
Poster de conférence
hal-00876041v1
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ASIP Design for Multi-Standard Channel DecodersAdvanced Hardware Design for Error Correcting Codes, Springer, pp.151 - 175, 2014, 978-3-319-10568-0. ⟨10.1007/978-3-319-10569-7⟩
Chapitre d'ouvrage
hal-01170472v1
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ASIP design and prototyping for wireless communication applicationsAdvanced Applications of Rapid Prototyping Technology in Modern Engineering, InTech - Open Access Publisher, 2011
Chapitre d'ouvrage
hal-00699677v1
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Hardware/Software Co-designDesign of Systems on a Chip : Design and Test, Springer, pp.133 - 158, 2007, 978-0-387-32499-9. ⟨10.1007/0-387-32500-X_7⟩
Chapitre d'ouvrage
hal-02124753v1
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Hardware/Software CodesignReis Ricardo, Lubaszewski Marcelo, Jess Jochen A.G. Design of Systems on Chip, Design and test, Springer, pp.133-158, 2007
Chapitre d'ouvrage
hal-00265185v1
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Generic architecture platform for multiprocessor system-on-chip designArchitecture and Design of Distributed Embedded Systems, kluwer academic publishers, pp.53-63, 2001, 978-0-387-35409-5
Chapitre d'ouvrage
hal-01467243v1
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Framework for system design, validation and fast prototyping of multiprocessor SoCsArchitecture and Design of Distributed Embedded Systems Series: IFIP International Federation for Information Processing,, Kluwer Academic Publishers, 2001, Vol. 61
Chapitre d'ouvrage
hal-00016207v1
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Models for the control of the test and of the reconfiguration of a computerTrappl,-R.; Hanika,-F.; Pichler,-F.-R. Progress-in-cybernetics-and-systems-research,, Wiley, Chichester, UK, xv+683 p., pp.410-8, 1979, vol.V
Chapitre d'ouvrage
hal-00016206v1
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Enabling 5G new services – Post-OFDM waveforms2016
Autre publication scientifique
hal-01874477v1
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FBMC-OQAM, a candidate waveform for 5G2015
Autre publication scientifique
hal-01874482v1
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New candidate waveform for 5G2015
Autre publication scientifique
hal-01873285v1
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Flexible FBMC air interface for 5G2015
Autre publication scientifique
hal-01873296v1
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Exploration et conception systématique d'architectures multiprocesseurs monopuces dédiées à des applications spécifiques = methods and tools for multiprocessor systems on chip, hardware/software co-designExploration and Systematic Design of Application-Specific Heterogeneous Multiprocessor SoCAutre [cs.OH]. Institut National Polytechnique de Grenoble - INPG, 2002. Français. ⟨NNT : ⟩
Thèse
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