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AB
Ahmed Ben Atitallah
Associate Professor
39
Documents
Affiliations actuelles
- 1150440
- 470004
Identifiants chercheurs
ahmed-ben-atitallah-
0000-0002-2121-4417
- Google Scholar : https://scholar.google.com/citations?user=0fn_DloAAAAJ&hl=fr
- IdRef : 124941141
Présentation
Ahmed Ben Atitallah received his Ph.D. degree in Electronics from the University of Bordeaux1 in 2007, France and the HDR Degree in 2013. He is currently an Associate Professor in Electronics at College of Engineering, Jouf University, Kingdom of Saudi Arabia. His main research activities are focused on image and video processing, Algorithm-Architecture Matching, Artificial Intelligence, SoC/SoPC architecture.
Domaines de recherche
Architectures Matérielles [cs.AR]
Traitement des images [eess.IV]
Sciences de l'ingénieur [physics]
Publications
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Architecture and HW/SW validation of nonlinear Border-Preserving InterpolatorDTIS: International Conference on Design & Technology of Integrated Systems in Nanoscale, May 2012, Gammarth, Tunisia. ⟨10.1109/DTIS.2012.6232968⟩
Communication dans un congrès
hal-01306335v1
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Implémentation matérielle du filtre anti-bloc pour la norme H.264/AVCGRETSI: Conférence francophone de la communauté du traitement du signal et des images, Sep 2011, Bordeaux, France
Communication dans un congrès
hal-01306342v1
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Performance analysis and evaluation of Xenomai with H.264/AVC decoderICM: International Conference on Microelectronics, Dec 2011, Hammamet, Tunisia. pp 1-6
Communication dans un congrès
hal-00655237v1
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Evaluation des performances de Xenomai avec un décodeur H.264/AVCColloque national du GDR SOC-SIP, Jun 2011, Lyon, France. pp 1-2
Communication dans un congrès
hal-00601828v1
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A parallel hardware architecture of deblocking filter in H264/AVCISETC: IEEE International Symposium on Electronics and Telecommunications, Nov 2010, Timisoara, Romania. pp 341-344, ⟨10.1109/ISETC.2010.5679363⟩
Communication dans un congrès
hal-00534913v1
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FPGA implementation of Vector Directional Distance FilterDTIS: IEEE International Conference on Design & Technology of Integrated Systems in Nanoscal Era, Mar 2010, Hammamet, Tunisia. pp 121-124, ⟨10.1109/DTIS.2010.5487600⟩
Communication dans un congrès
hal-00463175v1
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Design Implementation on FPGA of H.264/AVC Intra Decision FrameDTIS: IEEE International Conference on Design & Technology of Integrated Systems in Nanoscal Era, Mar 2010, Hammamet, Tunisia. pp 139-142, ⟨10.1109/DTIS.2010.5487540⟩
Communication dans un congrès
hal-00463882v1
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An FPGA Implementation of Motion Estimation Algorithm for H.264/AVCISIVC: IEEE International Symposium on Image/Video Communications and Mobile Networks, Sep 2010, Rabat, Morocco. pp 1-6, ⟨10.1109/ISVC.2010.5654826⟩
Communication dans un congrès
hal-00522140v1
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An Efficient Hardware Implementation of H.264 TQ/IQT ModuleISETC: IEEE International Symposium on Electronics and Telecommunications, Nov 2010, Timisoara, Romania. pp 337-340, ⟨10.1109/ISETC.2010.5679248⟩
Communication dans un congrès
hal-00534912v1
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Hardware Implementation And Experiment Validation Of The Vddrhf Color Image FilterSSD: IEEE International Conference on Systems Signals and Devices, Jun 2010, Amman, Jordan. pp. 1-4, ⟨10.1109/SSD.2010.5585526⟩
Communication dans un congrès
hal-00501834v1
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IMPLEMENTATION D’UN SYSTEME MATERIEL/LOGICIEL POUR LE FILTRAGE DES IMAGES COULEURSAMINA, Nov 2010, Monastir, Tunisie
Communication dans un congrès
hal-01306345v1
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Hardware Architecture for H.264/AVC INTRA 16X16 Frame ProcessingDTIS: IEEE International Conference on Design & Technology of Integrated Systems in Nanoscal Era, Apr 2009, Cairo, Egypt. pp. 82-85, ⟨10.1109/DTIS.2009.4938029⟩
Communication dans un congrès
hal-00405442v1
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FPGA Codesign Implementation of Vector Directional FilterIPTTA: IEEE Workshop on Image Processing Theory, Tools and Application, Nov 2008, Sousse, Tunisia. pp 1-5, ⟨10.1109/IPTA.2008.4743773⟩
Communication dans un congrès
hal-00342695v1
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Vector Median Rational Hybrid Filter implemented in HW/SW DesignICESCA: International Conference on Embedded Systems & Critical Applications, May 2008, Tunis, Tunisia
Communication dans un congrès
hal-00315733v1
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An Efficient Hardware Architecture Design for H.264/AVC intra 4X4 AlgorithmIDT: IEEE International Design and Test Workshop, Dec 2008, Monastir, Tunisia. pp. 173 - 176, ⟨10.1109/IDT.2008.4802491⟩
Communication dans un congrès
hal-00349249v1
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HW/SW FPGA Implementation of Vector Median FilterPRIME: IEEE Conference on Ph.D. Research in Microelectronics and Electronics, Jul 2007, Bordeaux, France. pp 101-104, ⟨10.1109/RME.2007.4401821⟩
Communication dans un congrès
hal-00315723v1
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Configurable Instruction Architecture for I/IQ on the Altera NIOS II ProcessorDASIP: Workshop on Design and Architectures for Signal and Image Processing, Nov 2007, Grenoble, France
Communication dans un congrès
hal-00315729v1
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Efficient Implementation of the H.264 Video Encoder on Embedded ProcessorSSD: IEEE International Conference on Systems Signals and Devices, Mar 2007, Hammamet, Tunisia
Communication dans un congrès
hal-00315721v1
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A configurable HW/SW Plateform for Video ApplicationIP/SoC: IP Based SoC Design Conference, Dec 2007, Grenoble, France. pp 289-292
Communication dans un congrès
hal-00315732v1
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De l'usage des processeurs softcore et de Linux pour la conception des systèmes embarquésCETSIS: Colloque sur l'Enseignement des Technologies et des Sciences de l'Information et des Systèmes, Oct 2007, Bordeaux, France
Communication dans un congrès
hal-00315727v1
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HW/SW FPGA Architecture for a Flexible Motion EstimationICECS: IEEE International Conference on Electronics Circuits and Systems, Dec 2007, Marrakech, Morocco. pp 30-33, ⟨10.1109/ICECS.2007.4510923⟩
Communication dans un congrès
hal-00315731v1
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An Efficient HW/SW Implementation of the H.263 Video Coder in FPGAICECS: IEEE International Conference on Electronics Circuits and Systems, Dec 2006, Nice, France. pp. 814-817, ⟨10.1109/ICECS.2006.379913⟩
Communication dans un congrès
hal-00315718v1
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HW/SW Codesign of the H. 263 Video Coderccece: Canadian Conference on Electrical and Computer Engineering , May 2006, ottawa, Canada. ⟨10.1109/CCECE.2006.277632⟩
Communication dans un congrès
hal-01306422v1
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Optimization and implementation on FPGA of the DCT/IDCT algorithmICASSP: IEEE International Conference on Acoustics, Speech and Signal Processing, May 2006, Toulouse, France. pp 928-931, ⟨10.1109/ICASSP.2006.1660807⟩
Communication dans un congrès
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L'enseignement des systèmes numériques complexesCETSIS: Colloque sur l'Enseignement des Technologies et des Sciences de l'Information et des Systèmes, Oct 2005, Nancy, France. pp 136-141
Communication dans un congrès
hal-00315715v1
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REAL-TIME VIDEO SYSTEM DESIGN BASED ON THE NIOS II PROCESSOR AND μCLINUXIP-SOC, Dec 2005, Grenoble, France
Communication dans un congrès
hal-01306423v1
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L'enseignement des systèmes numériques complexesCETSIS 2005, Oct 2005, Nancy, France. pp.41
Communication dans un congrès
hal-00404028v1
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Hardware platform design for real-time video applicationsICM: International Conference on Microelectronics, Dec 2004, tunis, Tunisia. ⟨10.1109/ICM.2004.1434768⟩
Communication dans un congrès
hal-01306425v1
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An FPGA Implementation of HW/SW Codesign Architecture for H.263 Video CodingEffective Video Coding for Multimedia Applications, InTech, pp 229-254, 2011
Chapitre d'ouvrage
hal-00638697v1
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Mise en oeuvre de Linux embarqué sur processeur softcore libre LEON2010, pp 48-57
Autre publication scientifique
hal-00463204v1
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Linux et les systèmes embarqués multimédia2007
Autre publication scientifique
hal-01306432v1
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