Abdoulaye Gamatié
16
Documents
Présentation
**Biography:** Abdoulaye Gamatié is currently a CNRS Senior Researcher (Directeur de Recherche [CNRS](http://www.cnrs.fr/index.php)) in the Microelectronics department of the [LIRMM](http://www.lirmm.fr/lirmm_eng) laboratory (Montpellier - France). His research activity focuses on the design of energy-efficient multicore/multiprocessor architectures for embedded and high-performance computing. He is the scientific leader of the French ANR project [CONTINUUM](http://www.lirmm.fr/continuum-project). He co-authored more than 50 articles in refereed journals and international conferences. He is the author of a [reference book](http://www.springer.com/engineering/circuits+%26+systems/book/978-1-4419-0940-4) on synchronous programming of embedded applications using the Signal language. He also contributed to several books as editor and chapter author. He is currently Associate Editor of ACM Transactions on Embedded Computing Systems (ACM TECS). He received his Habilitation (HDR in French) and Ph.D. in Computer Science, respectively in 2012 from Université de Lille 1 and in 2004 from Université de Rennes 1. He was previously member of [LIFL](http://www.lifl.fr/)computer science laboratory (Villeneuve D'Ascq - France) and [Inria](http://www.inria.fr/index.en.html) Lille - Nord Europe research center (France) from 2006 to 2012. Before this period, he had been member of [IRISA](http://www.irisa.fr/en) computer science laboratory (Rennes - France) where he worked on multi-clock synchronous design and analysis of real-time embedded systems in the avionics domain from 1999 to 2005.
Publications
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A gem5 trace-driven simulator for fast architecture exploration of OpenMP workloadsMicroprocessors and Microsystems: Embedded Hardware Design , 2019, 67, pp.42-55. ⟨10.1016/j.micpro.2019.01.008⟩
Article dans une revue
lirmm-02100235v1
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Automatic Energy-Efficiency Monitoring of OpenMP WorkloadsReCoSoC 2019 - 14th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, Jul 2019, York, United Kingdom. pp.43-50, ⟨10.1109/ReCoSoC48741.2019.9034988⟩
Communication dans un congrès
lirmm-02183901v1
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Improving the Performance of STT-MRAM LLC through Enhanced Cache Replacement PolicyARCS: Architecture of Computing Systems, Apr 2018, Braunschweig, Germany. pp.168-180, ⟨10.1007/978-3-319-77610-1_13⟩
Communication dans un congrès
lirmm-01669254v2
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Evaluation of Heterogeneous Multicore Cluster Architectures Designed for Mobile ComputingReCoSoC: Reconfigurable Communication-centric Systems-on-Chip, Jul 2018, Lille, France. ⟨10.1109/ReCoSoC.2018.8449376⟩
Communication dans un congrès
lirmm-01871273v1
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Efficient Programming for Multicore Processor Heterogeneity: OpenMP versus OmpSsOpenSuCo, Jun 2017, Frankfurt, Germany
Communication dans un congrès
lirmm-01723762v1
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ElasticSimMATE: a Fast and Accurate gem5 Trace-Driven Simulator for Multicore SystemsReCoSoC: Reconfigurable Communication-centric Systems-on-Chip, Jul 2017, Madrid, Spain. ⟨10.1109/ReCoSoC.2017.8016146⟩
Communication dans un congrès
hal-01723789v1
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Performance and Energy Assessment of Last-Level Cache Replacement PoliciesEDiS: Embedded and Distributed Systems, Dec 2017, Oran, Algeria. ⟨10.1109/EDIS.2017.8284032⟩
Communication dans un congrès
lirmm-01651247v1
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MAGPIE: System-level Evaluation of Manycore Systems with Emerging Memory TechnologiesEMS: Emerging Memory Solutions, Mar 2017, Lausanne, Switzerland
Communication dans un congrès
lirmm-01467328v1
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Flot automatique d’évaluation pour l’exploration d’architectures à base de mémoires non volatilesComPAS: Conférence en Parallélisme, Architecture et Système, Jul 2016, Lorient, France
Communication dans un congrès
lirmm-01345975v1
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OpenMP scheduling on ARM big.LITTLE architectureMULTIPROG 2016 - 9th International Workshop on Programmability and Architectures for Heterogeneous Multicores, HIPEAC, Jan 2016, Prague, Czech Republic
Communication dans un congrès
lirmm-01377630v1
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Full-System Simulation of big.LITTLE Multicore Architecture for Performance and Energy ExplorationMCSoC: Embedded Multicore/Many-core Systems-on-Chip, Sep 2016, Lyon, France. pp.201-208, ⟨10.1109/MCSoC.2016.20⟩
Communication dans un congrès
lirmm-01418745v1
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Loop Optimization in Presence of STT-MRAM Caches: a Study of Performance-Energy TradeoffsPATMOS: Power and Timing Modeling, Optimization and Simulation, Sep 2016, Bremen, Germany. pp.162-169, ⟨10.1109/PATMOS.2016.7833682⟩
Communication dans un congrès
hal-01347354v1
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Towards a Flexible and Comprehensive Evaluation Approach for Adressing NVM Integration in Cache Hierarchy2021
Pré-publication, Document de travail
lirmm-03341602v1
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Performance and Energy Impact of Enhanced Cache Replacement Policy on STT-MRAM LLC2021
Pré-publication, Document de travail
lirmm-03341604v1
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Deliverable D5.1 – Technical description of the holistic design flow in CONTINUUM[Research Report] Inria Rennes – Bretagne Atlantique; LIRMM (UM, CNRS); Cortus S.A.S. 2019
Rapport
lirmm-03168363v1
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Deliverable D3.2 - Evaluation of selected memory and communication technologies and exploitation opportunities in compilation and runtime management[Research Report] LIRMM (UM, CNRS); Inria Rennes – Bretagne Atlantique. 2017
Rapport
lirmm-03168318v1
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