Abdoulaye Gamatié
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Documents
Présentation
**Biography:** Abdoulaye Gamatié is currently a CNRS Senior Researcher (Directeur de Recherche [CNRS](http://www.cnrs.fr/index.php)) in the Microelectronics department of the [LIRMM](http://www.lirmm.fr/lirmm_eng) laboratory (Montpellier - France). His research activity focuses on the design of energy-efficient multicore/multiprocessor architectures for embedded and high-performance computing. He is the scientific leader of the French ANR project [CONTINUUM](http://www.lirmm.fr/continuum-project). He co-authored more than 50 articles in refereed journals and international conferences. He is the author of a [reference book](http://www.springer.com/engineering/circuits+%26+systems/book/978-1-4419-0940-4) on synchronous programming of embedded applications using the Signal language. He also contributed to several books as editor and chapter author. He is currently Associate Editor of ACM Transactions on Embedded Computing Systems (ACM TECS). He received his Habilitation (HDR in French) and Ph.D. in Computer Science, respectively in 2012 from Université de Lille 1 and in 2004 from Université de Rennes 1. He was previously member of [LIFL](http://www.lifl.fr/)computer science laboratory (Villeneuve D'Ascq - France) and [Inria](http://www.inria.fr/index.en.html) Lille - Nord Europe research center (France) from 2006 to 2012. Before this period, he had been member of [IRISA](http://www.irisa.fr/en) computer science laboratory (Rennes - France) where he worked on multi-clock synchronous design and analysis of real-time embedded systems in the avionics domain from 1999 to 2005.
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Partial Worst-Case Execution Time AnalysisComPAS: Conférence en Parallélisme, Architecture et Système, Jul 2018, Toulouse, France. pp.1-8
Communication dans un congrès
hal-01803006v1
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Compile-Time Silent-Store Elimination for Energy Efficiency: an Analytic Evaluation for Non-Volatile Cache MemoryRAPIDO: Rapid Simulation and Performance Evaluation, HiPEAC, Jan 2018, Manchester, United Kingdom. pp.1-8, ⟨10.1145/3180665.3180666⟩
Communication dans un congrès
hal-01660686v1
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Energy-Efficient Memory Mappings based on Partial WCET Analysis and Multi-Retention Time STT-RAMRTNS: Real-Time Networks and Systems, Oct 2018, Poitiers, France. pp.148-158, ⟨10.1145/3273905.3273908⟩
Communication dans un congrès
hal-01871320v1
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How Could Compile-Time Program Analysis help Leveraging Emerging NVM Features?EDiS: Embedded and Distributed Systems, Dec 2017, Oran, Algeria. pp.1-6, ⟨10.1109/EDIS.2017.8284031⟩
Communication dans un congrès
hal-01655195v1
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Loop Optimization in Presence of STT-MRAM Caches: a Study of Performance-Energy TradeoffsPATMOS: Power and Timing Modeling, Optimization and Simulation, Sep 2016, Bremen, Germany. pp.162-169, ⟨10.1109/PATMOS.2016.7833682⟩
Communication dans un congrès
hal-01347354v1
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Deliverable D5.1 – Technical description of the holistic design flow in CONTINUUM[Research Report] Inria Rennes – Bretagne Atlantique; LIRMM (UM, CNRS); Cortus S.A.S. 2019
Rapport
lirmm-03168363v1
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Deliverable D2.2 – Description of a specific optimization for low power[Research Report] Inria Rennes - Bretagne Atlantique; LIRMM (UM, CNRS). 2017
Rapport
lirmm-03168308v1
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Deliverable D3.2 - Evaluation of selected memory and communication technologies and exploitation opportunities in compilation and runtime management[Research Report] LIRMM (UM, CNRS); Inria Rennes – Bretagne Atlantique. 2017
Rapport
lirmm-03168318v1
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