Nombre de documents

20

CV de Abbas Sheibanyrad


Article dans une revue7 documents

  • Otavio Alcantara de Lima, Fresse, Virginie, Frederic Rousseau, A. Sheibanyrad. Synthesis of dependency-aware traffic generators from NoC simulation traces. Journal of Systems Architecture, Elsevier, 2016, 71. <hal-01440182>
  • Otávio Alcântara de Lima Jr, Virginie Fresse, Frederic Rousseau, Abbas Sheibanyrad. Synthesis of dependency-aware traffic generators from NoC simulation traces. Journal of Systems Architecture, Elsevier, 2016, 71, pp.102-113. <10.1016/j.sysarc.2016.10.004>. <hal-01451141>
  • Pascal Vivet, Yvain Thonnart, Romain Lemaire, Santos Cristiano, Edith Beigne, et al.. A 4 x 4 x 2 Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links. IEEE Journal of Solid-State Circuits, Institute of Electrical and Electronics Engineers, 2016, 52 (1), pp.33 - 49. <10.1109/JSSC.2016.2611497>. <hal-01447433>
  • Sahar Foroutan, Abbas Sheibanyrad, Frédéric Pétrot. Assignment of Vertical Links to Routers in Vertically-Partially-Connected 3D-NoCs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE, 2014, 33 (8), pp.1208-1218. <10.1109/TCAD.2014.2323219>. <hal-01195897>
  • F. Dubois, H. Sheibanyrad, F. Pétrot, M. Bahmani. Elevator-First: A Deadlock-Free Distributed Routing Algorithm for Vertically Partially Connected 3D-NoCs. IEEE Transactions on Computers, Institute of Electrical and Electronics Engineers, 2013, 62 (3), pp.609-615. <10.1109/TC.2011.239>. <hal-01138285>
  • Abbas Sheibanyrad, Alain Greiner. Two Efficient Synchronous ⇔ Asynchronous Converters well-suited for Networks-on-Chip in GALS Architectures. Integration, the VLSI Journal, Elsevier, 2008, 41 (1), pp.17-26. <10.1016/j.vlsi.2007.04.006>. <hal-01199004>
  • Abbas Sheibanyrad, Alain Greiner, Ivan Miro-Panades. Multisynchronous and Fully Asynchronous NoCs for GALS Architectures. IEEE Design & Test of Computers, Institute of Electrical and Electronics Engineers, 2008, 25 (6), pp.572-580. <10.1109/MDT.2008.167>. <hal-00367212>

Communication dans un congrès10 documents

  • F. Pétrot, S. Foroutan, H. Sheibanyrad. Cost-Efficient Buffer Sizing in Shared-Memory 3D-MPSoCs Using Wide I/O Interfaces. 5th Design for 3D Silicon Integration Workshop, Jun 2013, Grenoble, France. <hal-01059162>
  • M. Bahmani, H. Sheibanyrad, F. Pétrot, F. Dubois, P. Durante. A 3D-NoC Router Implementation Exploiting Vertically-Partially-Connected Topologies. IEEE Computer Society Annual Symposium on VLSI (ISVLSI'12), Aug 2012, Amherst, United States. pp.9-14, 2012, <10.1109/ISVLSI.2012.19>. <hal-00745456>
  • S. Foroutan, H. Sheibanyrad, F. Pétrot. Cost-efficient buffer sizing in shared-memory 3D-MPSoCs using wide I/O interfaces. The Design Automation Conference (DAC), Jun 2012, San Francisco, United States. ACM New York, NY, USA, pp.366-375, 2012, <10.1145/2228360.2228427>. <hal-00815811>
  • F. Darve, H. Sheibanyrad, P. Vivet, F. Pétrot. Physical Implementation of an Asynchronous 3D-NoC Router Using Serial Vertical Links. IEEE Computer Society Annual Symposium on VLSI (ISVLSI'11), 4-6 July, Jul 2011, Chennai, Tamil Nadu, India. IEEE Computer Society, pp.25 - 30, 2011, <10.1109/ISVLSI.2011.59>. <hal-00680437>
  • A. El Mrabti, A. Sheibanyrad, F. Rousseau, F. Pétrot, R. Lemaire, et al.. Abstract Description of System Application and Hardware Architecture for Hardware/Software Code Generation. 12th Euromicro Conference on Digital System Design (DSD'09), August 27-29, Aug 2009, Patras, Greece. IEEE Computer Society, pp.567 - 574, 2009. <hal-00421677>
  • Abbas Sheibanyrad, Alain Greiner. Hybrid-Timing FIFOs to use on Networks-on-Chip in GALS Architectures. ESA International Conference on Embedded Systems and Applications, Jun 2007, Las Vegas, Nevada, United States. CSREA Press, ESA International Conference on Embedded Systems and Applications, pp.27-33. <hal-01311526>
  • Abbas Sheibanyrad, Ivan Miro Panades, Alain Greiner. Systematic Comparison between the Asynchronous and the Multi-Synchronous Implementations of a Network on Chip Architecture. DATE Design Automation and Test in Europe Conference 2007, Apr 2007, Nice, France. IEEE, DATE Design Automation and Test in Europe Conference 2007, pp.1090-1095, <10.1109/DATE.2007.364439>. <hal-01311482>
  • Ivan Miro Panades, Alain Greiner, Abbas Sheibanyrad. A Low Cost Network-on-Chip with Guaranteed Service Well Suited to the GALS Approach. NanoNet International Conference on Nano-Networks, Sep 2006, Lausanne, Switzerland. IEEE, NanoNet International Conference on Nano-Networks, pp.1-5, <10.1109/NANONET.2006.346219>. <hal-01338441>
  • Abbas Sheibanyrad, Alain Greiner. Two Efficient Synchronous ⇔ Asynchronous Converters Well-Suited for Network on Chip in GALS Architectures. International Workshop on Power And Timing Modeling Optimization and Simulation, Sep 2006, Montpellier, France. Springer, International Workshop on Power And Timing Modeling Optimization and Simulation, 4148, pp.192-202, Lecture Notes in Computer Science. <10.1007/11847083_19>. <hal-01338438>
  • Ivan Miro Panades, Alain Greiner, Abbas Sheibanyrad. Micro-réseau sur puce compatible avec l'approche GALS. Journées Nationales du Réseau Doctoral de Micro-électronique, May 2006, Rennes, France. Journées Nationales du Réseau Doctoral de Micro-électronique, pp.1-5. <hal-01338238>

Direction d'ouvrage, Proceedings1 document

Chapitre d'ouvrage1 document

  • A. Sheibanyrad, F. Pétrot. Asynchronous 3D-NoCs Making Use of Serialized Vertical Links. Hamed Sheibanyrad, Frédéric Pétrot and Axel Jantsch. 3D Integration for NoC-based SoC Architectures, Springer, pp.149-165, 2011, Integrated Circuits and Systems, Part 3, <10.1007/978-1-4419-7618-5_7>. <hal-00564627>

Brevet1 document

  • F. Pétrot, A. Sheibanyrad. Architecture de communication à base de sérialiseur asynchrone entre circuits déposés sur des substrats de silicium empilés. France, Patent n° : 09/53637. 2009. <hal-00578021>