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80 résultats
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Models of Architecture[Research Report] PREESM/2015-12TR01, 2015, IETR/INSA Rennes; Scuola Superiore Sant’Anna, Pisa; Institut Pascal, Clermont Ferrand; University of Maryland, College Park; Tampere University of Technology, Tampere. 2015
Rapport
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CASSIS: Characterization with Adaptive Sample-Size Inferential Statistics Applied to Inexact CircuitsEUSIPCO: EUropean SIgnal Processing Conference, Sep 2018, Rome, Italy. ⟨10.23919/eusipco.2018.8553451⟩
Communication dans un congrès
hal-01879628v2
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SCAPE: HW-Aware Clustering of Dataflow Actors for Tunable Scheduling ComplexityDASIP 2023 - Workshop on Design and Architectures for Signal and Image Processing, HiPEAC, Jan 2023, Toulouse, France. pp.3-14, ⟨10.1007/978-3-031-29970-4_1⟩
Communication dans un congrès
hal-04089941v1
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Modeling Nested for Loops with Explicit Parallelism in Synchronous DataFlow GraphsEmbedded Computer Systems: Architectures, Modeling, and Simulation, Jul 2019, Pythagorion, Samos Island, Greece. pp.269-280, ⟨10.1007/978-3-030-27562-4_19⟩
Communication dans un congrès
hal-02267487v2
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Dataflow Modeling for Reconfigurable Signal Processing SystemsHandbook of Signal Processing Systems, 3rd Edition, pp.787-824, 2019, ⟨10.1007/978-3-319-91734-4_22⟩
Chapitre d'ouvrage
hal-01899410v1
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Memory Study and Dataflow Representations for Rapid Prototyping of Signal Processing Applications on MPSoCsSignal and Image processing. INSA de Rennes, 2014. English. ⟨NNT : 2014ISAR0004⟩
Thèse
tel-01127297v1
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Automatic Generation of S-LAM Descriptions from UML/MARTE for the DSE of Massively Parallel Embedded SystemsRoger Lee. Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed Computing 2015, 612, Springer, pp.195-211, 2016, Studies in Computational Intelligence, 978-3-319-23509-7. ⟨10.1007/978-3-319-23509-7_14⟩
Chapitre d'ouvrage
hal-01252511v1
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CERBERO Cross-layer modEl-based fRamework for multi-oBjective dEsign of Reconfigurable systems in unceRtain hybRid envirOnments16th ACM International Conference on Computing Frontiers, CF 2019, Apr 2019, Alghero, Italy. pp.320-325, ⟨10.1145/3310273.3323436⟩
Communication dans un congrès
hal-02161022v1
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Delays and States in Dataflow Models of ComputationSAMOS XVIII, Jul 2018, Pythagorion, Greece. ⟨10.1145/3229631.3229645⟩
Communication dans un congrès
hal-01850252v1
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Energy-Efficient Actor Execution for SDF Application on Heterogeneous Architectures26th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2018, Mar 2018, Cambridge, United Kingdom. pp.486-493, ⟨10.1109/PDP2018.2018.00083⟩
Communication dans un congrès
hal-01834878v1
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Real-Time Low Power Software HEVC Decoder on Embedded GPP: A Side-by-Side ComparisonDesign and Architectures for Signal and Image Processing (DASIP), Sep 2015, Cracow, Poland
Communication dans un congrès
hal-01205912v1
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Adaptive Simulation-based Framework for Error Characterization of Inexact CircuitsMicroelectronics Reliability, 2019, 96, pp.60-70. ⟨10.1016/j.microrel.2019.02.007⟩
Article dans une revue
hal-02094908v1
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Model-Based Programming for Multi-Processor Platforms with TTool/DIPLODOCUS and OMCCommunications in Computer and Information Science, Model-Driven Engineering and Software Development, Springer, pp.56_81, 2019, ⟨10.1007/978-3-030-11030-7_4⟩
Chapitre d'ouvrage
hal-02288056v1
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Evaluation of Image Quality Assessment Metrics for Semantic Segmentation in a Machine-to-Machine Communication Scenario15th International Conference on Quality of Multimedia Experience (QoMEX), Jun 2023, Ghent, Belgium. pp.1-6, ⟨10.1109/QoMEX58391.2023.10178503⟩
Communication dans un congrès
hal-04091521v2
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Towards Machine Perception Aware Image Quality AssessmentIEEE 25th International Workshop on MultiMedia Signal Processing (MMSP 2023), Sep 2023, Poitiers, France. pp.1-6, ⟨10.1109/MMSP59012.2023.10337677⟩
Communication dans un congrès
hal-04205183v1
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Memory Analysis and Optimized Allocation of Dataflow Applications on Shared-Memory MPSoCsJournal of Signal Processing Systems, 2015, 80 (1), pp.19-37. ⟨10.1007/s11265-014-0952-6⟩
Article dans une revue
hal-01083576v2
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MDE-based Rapid DSE of multi-core embedded systems: The H.264 Decoder Case StudyJournal of Microelectronics, Electronic Components and Materials, 2016, 46 (4), pp.219--228
Article dans une revue
hal-01502348v1
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Smart Search Space Reduction for Approximate Computing: a Low Energy HEVC Encoder Case StudyJournal of Systems Architecture, 2017
Article dans une revue
hal-02136709v1
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A Distributed Framework for Low-Latency OpenVX over the RDMA NoC of a Clustered ManycoreIEEE High Performance Extreme Computing Conference (HPEC 2018), Sep 2018, Waltham, MA, United States. ⟨10.1109/hpec.2018.8547736⟩
Communication dans un congrès
hal-02049414v1
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A Fast and Fuzzy Functional Simulator of Inexact Arithmetic Operators for Approximate Computing SystemsGLSVLSI 2018, May 2018, Chicago, United States. ⟨10.1145/3194554.3194574⟩
Communication dans un congrès
hal-01812719v1
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Comparing Three Clustering-based Scheduling Methods for Energy-Aware Rapid Design of MP2SoCsJournal of Signal Processing Systems, 2018, 90 (4), pp.537-570. ⟨10.1007/s11265-017-1261-7⟩
Article dans une revue
hal-01761220v1
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Hardware/Software self-adaptation in CPS The CERBERO project approach19th International Conference on Embedded Computer Systems Architectures, Modeling, and Simulation, SAMOS 2019, Jul 2019, Pythagorion, Greece. pp.416-428, ⟨10.1007/978-3-030-27562-4_30⟩
Communication dans un congrès
hal-02309555v1
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On Exploiting Energy-Aware Scheduling Algorithms for MDE-Based Design Space Exploration of MP2SoC24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP 2016), Feb 2016, Heraklion, Greece. pp.643-650, ⟨10.1109/PDP.2016.110⟩
Communication dans un congrès
hal-01305971v1
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DAMHSE Programming heterogeneous MPSoCs with hardware acceleration using dataflow-based design space exploration and automated rapid prototypingMicroprocessors and Microsystems: Embedded Hardware Design , 2019, 71, pp.102882. ⟨10.1016/j.micpro.2019.102882⟩
Article dans une revue
hal-02309549v1
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Models of Architecture: Application to ESL Model-Based Energy Consumption Estimation[Research Report] IETR/INSA Rennes; Scuola Superiore Sant’Anna, Pisa; Institut Pascal; University of Maryland, College Park; Tampere University of Technology, Tampere. 2017
Rapport
hal-01464856v1
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Hierarchical Dataflow Model for Efficient Programming of Clustered Manycore Processors28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2017), Jul 2017, Seattle, WA, United States
Communication dans un congrès
hal-01564019v1
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Memory Bounds for the Distributed Execution of a Hierarchical Synchronous Data-Flow Graph12th International Conference on Embedded Computer Systems: Architecture, Modeling and Simulation (SAMOS XII), Jul 2012, Agios Konstantinos, Greece. pp.160
Communication dans un congrès
hal-00721335v1
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Numerical Representation of Directed Acyclic Graphs for Efficient Dataflow Embedded Resource AllocationACM Transactions on Embedded Computing Systems (TECS), 2019, 18 (5), pp.101. ⟨10.1145/3358225⟩
Article dans une revue
hal-02355636v1
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Demonstrating the SPIDER Runtime for Reconfigurable Dataflow Graphs Execution onto a DMA-based Manycore ProcessorIEEE International Workshop on Signal Processing Systems, Oct 2017, Lorient, France. 2017
Poster de conférence
hal-01637300v1
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Influence of Dataflow Graph Moldable Parameters on Optimization CriteriaDASIP 2022 - Workshop on Design and Architectures for Signal and Image Processing, Jun 2022, Budapest, Hungary. pp.83-95, ⟨10.1007/978-3-031-12748-9_7⟩
Communication dans un congrès
hal-03752645v1
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