Filtrer vos résultats
- 79
- 49
- 3
- 90
- 22
- 9
- 2
- 2
- 2
- 2
- 1
- 1
- 2
- 116
- 37
- 3
- 3
- 4
- 4
- 2
- 6
- 2
- 6
- 10
- 7
- 6
- 5
- 4
- 12
- 7
- 5
- 10
- 7
- 9
- 6
- 1
- 2
- 4
- 8
- 1
- 119
- 12
- 104
- 48
- 17
- 6
- 5
- 5
- 4
- 4
- 4
- 3
- 3
- 3
- 3
- 3
- 3
- 2
- 2
- 2
- 2
- 2
- 2
- 2
- 2
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 131
- 40
- 35
- 33
- 31
- 20
- 13
- 10
- 10
- 9
- 7
- 6
- 6
- 6
- 6
- 6
- 5
- 5
- 5
- 5
- 5
- 5
- 5
- 4
- 4
- 4
- 4
- 4
- 4
- 4
- 3
- 3
- 3
- 3
- 3
- 3
- 3
- 3
- 3
- 3
- 3
- 3
- 3
- 3
- 2
- 2
- 2
- 2
- 2
- 2
- 2
- 2
- 2
- 2
- 2
- 2
- 2
- 2
- 2
- 2
- 2
- 2
- 2
- 2
- 2
- 2
- 2
- 2
- 2
- 2
- 2
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
131 résultats
|
Implementation of a Fast Fourier Transform Algorithm onto a Manycore ProcessorConference on Design and Architectures for Signal and Image Processing (DASIP), Sep 2015, Cracow, Poland. ⟨10.1109/dasip.2015.7367270⟩
Communication dans un congrès
hal-01238833v1
|
||
|
Intégration de services vidéo Mpeg sur architectures parallèlesCalcul parallèle, distribué et partagé [cs.DC]. INSA RENNES, 2002. Français. ⟨NNT : 2002ISAR0008⟩
Thèse
tel-04292101v1
|
||
Manycore Embedded processors for portable, optimized and power efficient processing of methods for vision algorithmsEuropean Machine Vision Forum 2017 (EMVF), Sep 2017, Viennes, Austria
Communication dans un congrès
hal-02505927v1
|
|||
|
An Open Framework for Rapid Prototyping of Signal Processing ApplicationsEURASIP Journal on Embedded Systems, 2009, vol 2009, pp14
Article dans une revue
hal-00429312v1
|
||
Estimateur de mouvement temps réel multi-DSP pour l'encodage vidéo MPEG-4 AVC/H.264 haute définitionOct 2006, pp.NC
Communication dans un congrès
hal-00125363v1
|
|||
|
The Study of the impact of architecture design on cognitive radioProceedings of the 8th IEEE International Multi-Conference on Systems, Signals & Devices (SSD), Mar 2011, Sousse, Tunisia. pp.CD
Communication dans un congrès
hal-00661410v1
|
||
|
On Memory Reuse Between Inputs and Outputs of Dataflow ActorsACM Transactions on Embedded Computing Systems (TECS), 2016, 15 (2), pp.30. ⟨10.1145/2871744⟩
Article dans une revue
hal-01284333v1
|
||
|
A Fast Heuristic to Pipeline SDF GraphsEmbedded Computer Systems: Architectures, Modeling, and Simulation, Jul 2020, Pythagorion, Samos Island, Greece. pp.139-151, ⟨10.1007/978-3-030-60939-9_10⟩
Communication dans un congrès
hal-02993338v1
|
||
|
Buffer Merging Technique for Minimizing Memory Footprints of Synchronous Dataflow SpecificationsInternational Conference on Acoustics, Speech and Signal Processing (ICASSP), Apr 2015, Brisbane, Australia. pp.1111-1115, ⟨10.1109/icassp.2015.7178142⟩
Communication dans un congrès
hal-01146340v1
|
||
|
Generation of Efficient High-Level Hardware Code from Dataflow ProgramsDesign, Automation and test in Europe (DATE), Mar 2012, Dresden, Germany. pp.NC
Communication dans un congrès
hal-00763804v1
|
||
|
Relaxed Subgraph Execution Model for the Throughput Evaluation of IBSDF GraphsInternational Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), Jul 2017, SAMOS, Greece. ⟨10.1109/SAMOS.2017.8344630⟩
Communication dans un congrès
hal-01569593v1
|
||
|
Demonstrating a Dataflow-based RTOS for Heterogeneous MPSoC by means of a Stereo Matching ApplicationDASIP 2014, Oct 2014, Madrid, Spain
Communication dans un congrès
hal-01101788v1
|
||
|
A comparison of cost construction methods onto a C6678 platform for stereo matching2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), Oct 2016, Rennes, France. ⟨10.1109/DASIP.2016.7853821⟩
Communication dans un congrès
hal-01420790v1
|
||
|
Software synthesis of CAL actors for the MPEG reconfigurable Video Coding frameworkImage Processing, 2008. ICIP 2008. 15th IEEE International Conference on, Oct 2008, San Diego, United States. pp.1408 - 1411, ⟨10.1109/ICIP.2008.4712028⟩
Communication dans un congrès
hal-00336481v1
|
||
|
A codesign synthesis from an MPEG-4 decoder dataflow descriptionCircuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on, May 2010, Paris, France. pp.1995 -1998, ⟨10.1109/ISCAS.2010.5537107⟩
Communication dans un congrès
hal-00560031v1
|
||
|
Building a RTOS for MPSoC Dataflow Programming2011 International Symposium on System on Chip (SoC), Oct 2011, Finland. pp.143
Communication dans un congrès
hal-00658848v1
|
||
SynDEx executive kernel development for DSPs TI C6x applied to real-time and embedded multiprocessors architectures2002, Volume II pp 213-216
Communication dans un congrès
hal-00124987v1
|
|||
|
PREESM: A Dataflow-Based Rapid Prototyping Framework for Simplifying Multicore DSP ProgrammingEDERC, Sep 2014, Italy. pp.36
Communication dans un congrès
hal-01059313v1
|
||
|
Automated Clustering and Pipelining of Dataflow Actors for Controlled Scheduling ComplexityEUSIPCO, EURASIP, Sep 2023, Helsiinki, Finland
Communication dans un congrès
hal-04253298v1
|
||
|
PiMM: Parameterized and Interfaced dataflow Meta-Model for MPSoCs runtime reconfiguration13th International Conference on Embedded Computer Systems: Architecture, Modeling and Simulation (SAMOS XIII), Jul 2013, Samos, Greece. pp.41 - 48, ⟨10.1109/SAMOS.2013.6621104⟩
Communication dans un congrès
hal-00877492v2
|
||
|
AN EXPERIMENTAL TOOLCHAIN BASED ON HIGH-LEVEL DATAFLOW MODELS OF COMPUTATION FOR HETEROGENEOUS MPSOCDASIP, Oct 2012, Karlsruhe, Germany
Communication dans un congrès
hal-00749175v1
|
||
|
Reconfigurable Video Coding on multicore : an overview of its main objectivesIEEE Signal Processing Magazine, 2009, Volume 26 (Issue 6), pp 113 - 123. ⟨10.1109/MSP.2009.934107⟩
Article dans une revue
hal-00429360v1
|
||
Automatic Coarse-Grain Partitioning and Automatic Code Generation for Heterogeneous ArchitecturesSignal Processing Systems, 2003. SIPS'03. IEEE Workshop on, 2003, South Korea. pp.316-321
Communication dans un congrès
hal-00124965v1
|
|||
Intégration d'un décodeur Mpeg-4 sur architecture multi-C6x2002, pp.CD
Communication dans un congrès
hal-00124983v1
|
|||
AVSynDEx: A Rapid Prototyping Process Dedicated to the Implementation of Digital Image Processing Applications on multi-DSPs and FPGA ArchitecturesEurasip Journal on Applied Signal Processing, 2002, Vol. 2002 N°9, pp.990-1002
Article dans une revue
hal-00125129v1
|
|||
Développement d'un codec Vidéo MPEG-4 temps-réel embarqués sur architectures distribuéesInternational Symposium on Image/Video Communications (ISIVC), 2004, Brest, France. pp.NC
Communication dans un congrès
hal-00125019v1
|
|||
|
Automatic Code Generation For Multi-Microblaze System With SynDEx15th European Signal Processing Conference (Eusipco 2007), Sep 2007, Poznań, Poland. pp.ISBN: 978-83-921340-2-2
Communication dans un congrès
hal-00171790v1
|
||
Automatic Code generation for Interconnected distributed RAM in the AAA Methodology: H264 Motion Estimation Case StudyWorkshop on Design and Architectures for Signal and Image Processing (DASIP), Nov 2007, Grenoble, France. ppXX
Communication dans un congrès
hal-00176973v1
|
|||
Génération automatique de code distribué à l'aide de RTOS : application au codage d'images LARCOmpression et REprésentation des Signaux Audiovisuels (CORESA), Oct 2006, France. pp.NC
Communication dans un congrès
hal-00125355v1
|
|||
|
Adaptive Multicore Scheduling for the LTE UplinkNASA/ESA Conference on Adaptive Hardware and Systems (Ahs 2010), Jun 2010, Anaheim, United States
Communication dans un congrès
hal-00488576v1
|