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148 résultats
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Bound the Peak Performance of SGEMM on GPU with software-controlled fast memory[Research Report] RR-7923, INRIA. 2012
Rapport
hal-00686006v2
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Break Down GPU Execution Time with an Analytical MethodRapido '12, Jan 2012, Paris, France. ⟨10.1145/2162131.2162136⟩
Communication dans un congrès
hal-00764874v1
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Intercepting Functions for Memoization: A Case Study Using Transcendental FunctionsACM Transactions on Architecture and Code Optimization, 2015, 12 (2), pp.23. ⟨10.1145/2751559⟩
Article dans une revue
hal-01178085v1
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An Empirical High Level Performance Model For Future Many-coresProceedings of the 12th ACM International Conference on Computing Frontiers, 2015, Ischia, Italy. ⟨10.1145/2742854.2742867⟩
Communication dans un congrès
hal-01170038v1
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Skewed-associative caches[Research Report] RR-1655, INRIA. 1992
Rapport
inria-00074902v1
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HArdware Volatile Entropy Gathering and Expansion: generating unpredictable random number at user level[Research Report] RR-4592, INRIA. 2002
Rapport
inria-00071993v1
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A case for (partially) tagged geometric history length branch predictionThe Journal of Instruction-Level Parallelism, 2006, 8, pp.23
Article dans une revue
hal-03408381v1
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BADCO: Behavioral Application-Dependent Superscalar Core ModelSAMOS XII: International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, Jul 2012, Samos, Greece
Communication dans un congrès
hal-00707346v1
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Cost-Effective Speculative Scheduling in High Performance ProcessorsInternational Symposium on Computer Architecture, ACM/IEEE, Jun 2015, Portland, United States. pp.247-259, ⟨10.1145/2749469.2749470⟩
Communication dans un congrès
hal-01193233v1
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A Comprehensive Study of Dynamic Global History Branch Prediction[Research Report] RR-4219, INRIA. 2001
Rapport
inria-00072400v1
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Yet Another Compressed Cache: a Low Cost Yet Effective Compressed CacheACM Transactions on Architecture and Code Optimization, 2016, 13, pp.1-25. ⟨10.1145/2976740⟩
Article dans une revue
hal-01354248v1
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Compile-Time Function Memoization26th International Conference on Compiler Construction, Feb 2017, Austin, United States
Communication dans un congrès
hal-01423811v1
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Value Speculation through Equality PredictionICCD 2019 - 37th IEEE International Conference on Computer Design, Nov 2019, Abu Dhabi, United Arab Emirates. pp.1-4
Communication dans un congrès
hal-02383480v1
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Transforming TLP into DLP with the Dynamic Inter-Thread Vectorization Architecture[Research Report] RR-8830, Inria Rennes Bretagne Atlantique. 2015
Rapport
hal-01244938v1
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Selecting Benchmark Combinations for the Evaluation of Multicore ThroughputInternational Symposium on Performance Analysis of Systems and Software, Apr 2013, Austin, United States. ⟨10.1109/ISPASS.2013.6557168⟩
Communication dans un congrès
hal-00788824v1
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GCDS: A Compiler Strategy for Trading Code Size Against Performance in Embedded Applications[Research Report] RR-3346, INRIA. 1998
Rapport
inria-00073343v1
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Understanding cache attacks[Research Report] RR-5881, INRIA. 2006
Rapport
inria-00071387v1
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CASH Design Space Exploration[Research Report] RR-5994, INRIA. 2006
Rapport
inria-00105284v3
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Don't Use the Page Number, but a Pointer on It[Research Report] RR-2727, INRIA. 1995
Rapport
inria-00073967v1
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Évolution des gammes de processeurs MIPS, DEC Alpha, PowerPC, SPARC, x86 et PA-RISC[Rapport de recherche] RR-3188, INRIA. 1997
Rapport
inria-00073501v1
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SIMT-X: Extending Single-Instruction Multi-Threading to Out-of-Order CoresACM Transactions on Architecture and Code Optimization, 2020, 17 (2), pp.15. ⟨10.1145/3392032⟩
Article dans une revue
hal-02542333v1
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The FNL+MMA Instruction Cache PrefetcherIPC-1 - First Instruction Prefetching Championship, May 2020, Valence, Spain. pp.1-5
Communication dans un congrès
hal-02884880v1
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Decoupled Zero-Compressed MemoryHiPEAC - International Conference on High-Performance and Embedded Architectures and Compilers, Jan 2011, Heraklion, Greece. ⟨10.1145/1944862.1944876⟩
Communication dans un congrès
inria-00529332v1
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Fairness Metrics for Multithreaded ProcessorsIEEE Computer Architecture Letters, 2011, IEEE Computer Architecture Letters 2011, ⟨10.1109/L-CA.2011.1⟩
Article dans une revue
inria-00564560v1
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TAGE-SC-L Branch PredictorsJILP - Championship Branch Prediction, Jun 2014, Minneapolis, United States
Communication dans un congrès
hal-01086920v1
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Practical Multidimensional Branch PredictionIEEE Micro, 2016, ⟨10.1109/MM.2016.33⟩
Article dans une revue
hal-01330510v1
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Les processeurs multicœurs aujourd’hui et demainInterstices, 2011
Article dans une revue
hal-01350165v1
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Cost Effective Physical Register SharingInternational Symposium on High Performance Computer Architecture, IEEE, Mar 2016, Barcelona, Spain. ⟨10.1109/HPCA.2016.7446105⟩
Communication dans un congrès
hal-01259137v2
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Dictionary Sharing: An Efficient Cache Compression Scheme for Compressed Caches MICRO 2016 - 49th Annual IEEE/ACM International Symposium on Microarchitecture, IEEE/ACM, Oct 2016, Taipei, Taiwan
Communication dans un congrès
hal-01354246v3
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Managing SMT Resource Usage through Speculative Instruction Window Weighting[Research Report] RR-7103, INRIA. 2009, pp.22
Rapport
inria-00433081v2
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